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| 1 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 future technology devices international ltd vinculum - ii embedded dua l usb host controller ic vinculum - ii is ftdis ? em bedded processor core ? 16 bit harvard architecture ? two full - speed or low - speed usb 2.0 interfaces capable of host or slave functions ? 256kbytes on - chip e - flash memory ( 128k x 16 - bits) ? 16kbytes on - chip data ram ( 4k x 32 - bits ? programmable uart up to 6 mbaud ? two spi (serial peripheral) slave interfaces and one spi master interface ? reduced power modes capability ? variable instruction length ? native support for 8, 16 and 32 bit data types ? eight bit wide fifo interface ? f irmware upgrades via uart, spi, and fifo interfa ce ? 12mhz oscillator using external crystal ? general - purpose timers ? +3.3v single supply operation with 5v safe inputs ? software development s uite of tools to create customised firmware . compiler linker C C ? available in six rohs compliant package s - 32 lqfp, 32 qfn, 48 lqfp, 48 qfn, 64 lqfp and 64 qfn ? vnc2 - 48l1 package option compatible with vnc1l - 1a ? 44 configurable i/o pins on the 64 pin device, 28 i/o pins on the 48 pin device and 12 i/o on the 32 pin device using the i/o multiplexer ? - 40c to + 8 5c extended operating temperature range ? simultaneous multiple file access on boms devices ? eight pulse width modulation outputs to allow connectivity with motor control applications ? debugger interface module ? system suspend modes use of ftdi devices in l ife support and/or safety applications is entirely at the users risk, and the user agrees to defend, indemnify and hold harmless ftdi from any and all damages, claims, suits or expense resulting from such use.
2 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 1 typical applications ? add usb host capabilit y to embedded products ? interface usb flash drive to mcu/pld/fpga C data storage and firmware updates ? usb flash drive data storage or firmware updates ? usb flash drive to usb flash drive file transfer interface ? digital camera to usb flash drive * ? pda to usb f lash drive * ? mp3 player to usb flash drive or other usb slave device interface ? osi wireless interface ? usb wireless process controller ? telecom system calls logging to replace printer log ? data logging ? mobile phone to usb flash drive* ? gps to mobile phone inter face ? instr umentation usb flash drive* ? data - logger usb flash drive* ? set top box - usb device interface ? gps tracker with usb flash disk storage ? usb webcam ? flash drive to sd card data transfer ? vending machine connectivity ? tlm serial converter ? geotagging of p hotos C gps location linked to image ? motorcycle system telemetry logging ? medical systems ? pwm applications for motor control applications e.g. toys ? fpga interfacing * or similar usb slave device interface e.g. usb external drive. 1.1 part numbers part number package vnc 2 - 64 l 64 pin lqfp vnc 2 - 64q 64 pin qfn vnc 2 - 48 l 48 pin lqfp vnc 2 - 48q 48 pin qfn vnc 2 - 32l 32 pin lqf p vnc 2 - 32q 32 pin qfn table 1 . 1 part numbers please refer to section 11 for all package mechanical parameters. 1.2 usb compliant at time of writing this data sheet, vnc2 has not completed usb compliancy testing. 3 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 2 vnc2 block diagram for a description of each function please refer to sect ion 4 . figure 2 . 1 simplified vnc2 block diagram u a r t u s b h o s t / d e v i c e c o n t r o l l e r s p i m a s t e r p w m s f i f o i n t e r f a c e s p i s l a v e 0 s p i s l a v e 1 g e n e r a l p u r p o s e t i m e r s g p i o s i n p u t / o u t p u t m u l t i p l e x e r u s b h o s t / d e v i c e c o n t r o l l e r p e r i p h e r a l b u s d m a 3 d m a 2 d a t a m e m o r y b u s 1 6 k b y t e s d a t a r a m ( 4 k x 3 2 ) e m b e d d e d c p u d e b u g g e r f l a s h p r o g r a m m e r d m a 1 d m a 0 u s b h o s t / d e v i c e t r a n s c e i v e r 0 u s b h o s t / d e v i c e t r a n s c e i v e r 1 u s b 1 d p u s b 1 d m u s b 2 d p u s b 2 d m d e b u g g e r i / f x t o u t x t i n o s c i l l a t o r / p l l i n t e r n a l c l o c k s a n d t i m e r s 3 2 b i t b u s 8 b i t b u s 2 5 6 k b y t e s e - f l a s h ( 6 4 k x 3 2 ) p r o g r a m m e m o r y b u s 4 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 table of contents 1 typical a pplications ................................ ................................ ... 2 1.1 part numbers ................................ ................................ ........................... 2 1.2 usb compliant ................................ ................................ ......................... 2 2 vnc2 bloc k diagram ................................ ................................ .. 3 3 device pin out and signal description summary ......................... 7 3.1 pin out - 32 pin lqfp ................................ ................................ ............. 7 3.2 pin out - 32 pin qfn ................................ ................................ ............... 8 3.3 pin out - 48 pin lqfp ................................ ................................ .............. 9 3.4 pin out - 48 pin qfn ................................ ................................ ............. 10 3.5 pin out - 64 pin lqfp ................................ ................................ ........... 11 3.6 pin out - 64 pin qfn ................................ ................................ ............. 12 3.7 vnc2 schematic sy mbol 32 pin ................................ ............................ 13 3.8 vnc2 schematic symbol 48 pin ................................ ............................ 14 3.9 vnc2 schematic symbol 64 pin ................................ ............................ 15 3.10 pin configuration usb and power ................................ ...................... 16 3.11 miscellaneous signals ................................ ................................ ......... 17 3.12 pin configuration input / outp ut ................................ ...................... 18 4 function description ................................ ................................ . 21 4.1 key features ................................ ................................ .......................... 21 4.2 function al block descriptions ................................ ............................... 21 4.2.1 embedded cpu ................................ ................................ ................................ .................. 21 4.2.2 flash module ................................ ................................ ................................ ...................... 21 4.2.3 flash programming module ................................ ................................ ................................ 21 4.2.4 input / output multiplexer module ................................ ................................ ...................... 22 4.2.5 peripheral dma modules 0, 1, 2 & 3 ................................ ................................ .................... 23 4.2.6 ram module ................................ ................................ ................................ ....................... 23 4.2.7 peripheral interface modules ................................ ................................ .............................. 23 4.2.8 us b transceivers 0 and 1 ................................ ................................ ................................ .. 23 4.2.9 usb host / device controllers ................................ ................................ ............................ 23 4.2.10 12mhz oscillator ................................ ................................ ................................ ............ 23 4.2.11 power saving modes and standby mode. ................................ ................................ ........ 23 5 i/o multiplexer ................................ ................................ ........ 24 5.1 i/o peripherals signal names ................................ .............................. 29 5.2 i/o multiplexer configuration ................................ .............................. 30 5.3 i/o mux group 0 ................................ ................................ .................... 31 5.4 i/o mux group 1 ................................ ................................ .................... 32 5 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 5.5 i/o mux group 2 ................................ ................................ .................... 33 5.6 i/o mux group 3 ................................ ................................ .................... 34 5.7 i/o mux interface configuration example ................................ ........... 35 6 peripheral interfaces ................................ ................................ 36 6.1 uart interface ................................ ................................ ...................... 36 6.1.1 uart mode signal descriptions ................................ ................................ .......................... 37 6.2 serial peripheral interface C spi modes ................................ .............. 39 6.2.1 spi clock phase modes ................................ ................................ ................................ ....... 40 6.3 serial peripheral interface C slave ................................ ....................... 41 6.3.1 spi slave signal descriptions ................................ ................................ ............................. 42 6.3.2 full duplex ................................ ................................ ................................ ......................... 43 6.3.3 half duplex, 4 pin ................................ ................................ ................................ .............. 45 6.3.4 half duplex, 3 pin ................................ ................................ ................................ .............. 46 6.3.5 unmanaged mode ................................ ................................ ................................ .............. 47 6.3.6 vnc1l legacy interface ................................ ................................ ................................ ..... 48 6.4 serial peri pheral interface C spi master ................................ .............. 53 6.4.1 spi master signal descriptions. ................................ ................................ .......................... 53 6.5 debugger interface ................................ ................................ ............... 56 6.5.1 debugger interface signal description ................................ ................................ ................ 56 6.6 parallel fifo C asynchronous mode ................................ ..................... 57 6.6. 1 fifo signal descriptions ................................ ................................ ................................ .... 57 6.6.2 read / write transaction asynchronous fifo mode ................................ ............................ 59 6.7 parallel fifo C synchronous mode ................................ ....................... 61 6.7.1 read / write transaction synchronous fifo mode ................................ .............................. 62 6.8 general purpose timers ................................ ................................ ........ 63 6.9 pulse width modulation ................................ ................................ ......... 63 6.10 general purpose input output ................................ ........................... 64 7 usb interfaces ................................ ................................ ......... 65 8 firmware ................................ ................................ ................. 66 8.1 rtos ................................ ................................ ................................ ....... 66 8.2 device drivers ................................ ................................ ........................ 66 8.3 firmware C software development toolchain ................................ ..... 66 8.4 precompiled firmware ................................ ................................ .......... 67 9 device characteristic s and ratings ................................ ............ 68 9.1 absolute maximum ratings ................................ ................................ ... 68 9.2 dc characteristics ................................ ................................ ................. 69 9.3 esd and latch - up specifications ................................ .......................... 71 10 application examples ................................ ............................... 72 6 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 10.1 example vnc2 schematic (mcu C uart interface) .......................... 72 11 package parameters ................................ ................................ . 73 11.1 vnc2 package markings ................................ ................................ .... 73 11.2 vnc2, lqfp - 32 package dimensions ................................ ................. 74 11.3 vnc2, qfn - 32 package dimensions ................................ .................. 75 11.4 vnc2, lqfp - 48 package dimensions ................................ ................. 76 11.5 vnc2, qfn - 48 package dimensions ................................ .................. 77 11.6 vnc2, lqfp - 64 package dimensions ................................ ................. 78 11.7 vnc2, qfn - 64 package dimensions ................................ .................. 79 11.8 solder reflow profile ................................ ................................ .......... 80 12 contact information ................................ ................................ . 82 appendix a C references ................................ ................................ . 83 application, technical notes,toolchain download and precompiled romfile links ................................ ................................ ................................ ................. 83 acronyms and abbreviations ................................ ................................ .......... 84 appendix b C list of figures and tables ................................ ............ 85 list of tables ................................ ................................ ................................ ... 85 list of figures ................................ ................................ ................................ .. 85 appendix c C revision history ................................ .......................... 88 7 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 3 device pin out and signal description summary vnc2 is available in six packages: 32 pin lqfp, 32 pin qfn, 48 pin lqf p (pin compatible with vnc1l ), 48 pin qfn, 64 pin lqfp and 64 p in qfn . figure 3.3 shows how the vnc2 pins map to the vnc1l pins ( vnc2 pins labelled in bold te xt ): 3.1 pin out - 32 pin lqfp figure 3 . 1 32 pin lqfp C top down view f t d i x x x x x x x x x x v n c 2 - 3 2 l 1 a y y w w g n d c o r e u s b 1 d p u s b 1 d m u s b 2 d p u s b 2 d m v c c i o 3 . 3 v i o b u s 4 i o b u s 5 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 g n d c o r e i o b u s 6 i o b u s 7 i o b u s 8 i o b u s 1 1 i o b u s 1 0 i o b u s 9 v c c i o 3 . 3 v g n d c o r e 1 . 8 v v r e g o u t 1 . 8 v v c c p l l i n x t i n x t o u t g n d p l l 3 . 3 v v r e g i n n c r e s e t # p r o g # i o b u s 0 i o b u s 1 g n d i o v c c i o 3 . 3 v i o b u s 2 i o b u s 3 8 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 3.2 pin out - 32 pin qfn figure 3 . 2 32 pin qfn C top down view g n d c o r e 1 . 8 v v r e g o u t 1 . 8 v v c c p l l i n x t i n x t o u t g n d p l l 3 . 3 v v r e g i n n c 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 g n d c o r e i o b u s 6 i o b u s 7 i o b u s 8 i o b u s 1 1 i o b u s 1 0 i o b u s 9 v c c i o 3 . 3 v r e s e t # p r o g # i o b u s 0 i o b u s 1 g n d i o v c c i o 3 . 3 v i o b u s 2 i o b u s 3 g n d c o r e u s b 1 d p u s b 1 d m u s b 2 d p u s b 2 d m v c c i o 3 . 3 v i o b u s 4 i o b u s 5 f t d i x x x x x x x x x x v n c 2 - 3 2 q 1 a y y w w 9 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 3.3 pin out - 48 pin lqfp figure 3 . 3 48 pin lqfp C top down view i t a l i c t e x t = v n c 1 b o l d t e x t = v n c 2 f t d i x x x x x x x x x x v n c 2 - 4 8 l 1 a y y w w g n d a d b u s 6 a d b u s 7 a c b u s 0 a c b u s 7 a c b u s 6 a c b u s 5 a c b u s 4 a c b u s 3 a c b u s 2 a c b u s 1 v c c i o g n d c o r e i o b u s 1 8 i o b u s 1 9 i o b u s 2 0 i o b u s 2 7 i o b u s 2 6 i o b u s 2 5 i o b u s 2 4 i o b u s 2 3 i o b u s 2 2 i o b u s 2 1 v c c i o 3 . 3 v g n d b d b u s 2 b d b u s 5 b d b u s 4 b d b u s 3 v c c i o b d b u s 6 b d b u s 7 b c b u s 0 b c b u s 1 b c b u s 2 b c b u s 3 g n d i o i o b u s 2 i o b u s 5 i o b u s 4 i o b u s 3 v c c i o 3 . 3 v i o b u s 6 i o b u s 7 i o b u s 8 i o b u s 9 i o b u s 1 0 i o b u s 1 1 g n d v c c a v c c x t i n x t o u t a g n d p l l f l t r t e s t r e s e t # p r o g # b d b u s 0 b d b u s 1 g n d c o r e 3 . 3 v v r e g i n 1 . 8 v v c c p l l i n x t i n x t o u t g n d p l l 1 . 8 v v r e g o u t n c r e s e t # p r o g # i o b u s 0 i o b u s 1 g n d u s b 1 d p u s b 1 d m u s b 2 d p u s b 2 d m v c c i o a d b u s 0 a d b u s 1 a d b u s 2 a d b u s 3 a d b u s 4 a d b u s 5 g n d c o r e u s b 1 d p u s b 1 d m u s b 2 d p u s b 2 d m v c c i o 3 . 3 v i o b u s 1 2 i o b u s 1 3 i o b u s 1 4 i o b u s 1 5 i o b u s 1 6 i o b u s 1 7 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 1 4 3 5 7 6 8 9 1 1 1 0 1 2 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 5 3 6 3 3 3 4 3 2 3 0 3 1 2 9 2 8 2 6 2 7 2 5 10 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 3.4 pin out - 48 pin qfn figure 3 . 4 48 pin qfn C top down view g n d c o r e 3 . 3 v r e g i n 1 . 8 v c c p l l i n x t i n x t o u t g n d p l l 1 . 8 v r e g o u t n c r e s e t # p r o g # i o b u s 0 i o b u s 1 2 1 4 3 5 7 6 8 9 1 1 1 0 1 2 f t d i x x x x x x x x x x v n c 2 - 4 8 q 1 a y y w w i o b u s 2 i o b u s 3 i o b u s 4 i o b u s 5 v c c i o 3 . 3 v i o b u s 6 i o b u s 7 i o b u s 8 i o b u s 9 i o b u s 1 0 i o b u s 1 1 g n d i o 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 u s b 1 d m u s b 1 d p u s b 2 d p g n d c o r e v c c i o 3 . 3 v u s b 2 d m i o b u s 1 3 i o b u s 1 2 i o b u s 1 5 i o b u s 1 4 i o b u s 1 7 i o b u s 1 6 i o b u s 1 9 i o b u s 1 8 v c c i o 3 . 3 v g n d i o b u s 2 1 i o b u s 2 0 i o b u s 2 3 i o b u s 2 2 i o b u s 2 5 i o b u s 2 4 i o b u s 2 7 i o b u s 2 6 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 5 3 6 3 3 3 4 3 2 3 0 3 1 2 9 2 8 2 6 2 7 2 5 11 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 3.5 pin out - 64 pin lqfp figure 3 . 5 64 pin lqfp C top down view 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 g n d c o r e i o b u s 3 2 i o b u s 3 3 i o b u s 3 4 i o b u s 4 1 i o b u s 4 0 i o b u s 3 9 i o b u s 3 8 i o b u s 3 7 i o b u s 3 6 i o b u s 3 5 v c c i o 3 . 3 v g n d c o r e 3 . 3 v v r e g i n 1 . 8 v v c c p l l i n x t i n x t o u t g n d p l l 1 . 8 v v r e g o u t n c r e s e t # p r o g # i o b u s 0 i o b u s 1 g n d i o i o b u s 5 i o b u s 2 i o b u s 3 i o b u s 4 i o b u s 1 1 i o b u s 1 2 i o b u s 1 3 i o b u s 1 4 i o b u s 1 5 i o b u s 1 6 i o b u s 1 7 g n d c o r e u s b 1 d p u s b 1 d m u s b 2 d p u s b 2 d m v c c i o 3 . 3 v i o b u s 2 0 i o b u s 2 1 i o b u s 2 2 i o b u s 2 3 i o b u s 2 4 i o b u s 2 5 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 6 3 i o b u s 6 i o b u s 7 i o b u s 8 i o b u s 9 v c c i o 3 . 3 v i o b u s 1 0 i o b u s 1 8 i o b u s 1 9 i o b u s 2 8 i o b u s 2 7 i o b u s 2 6 i o b u s 2 9 i o b u s 3 0 i o b u s 3 1 i o b u s 4 3 i o b u s 4 2 f t d i x x x x x x x x x x v n c 2 - 6 4 l 1 a y y w w 6 4 12 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 3.6 pin out - 64 pin qfn figure 3 . 6 64 pin qfn C top down view 2 1 4 3 5 7 6 8 9 1 1 1 0 1 2 x t o u t g n d p l l 1 . 8 v r e g o u t n c r e s e t # p r o g # i o b u s 0 i o b u s 1 1 3 1 5 1 4 1 6 g n d c o r e 3 . 3 v r e g i n 1 . 8 v c c p l l i n x t i n i o b u s 2 i o b u s 3 i o b u s 4 i o b u s 5 i o b u s 8 i o b u s 9 v c c i o 3 . 3 v i o b u s 1 0 g n d i o 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 1 7 1 8 3 1 3 2 i o b u s 6 i o b u s 7 i o b u s 1 1 i o b u s 1 2 i o b u s 1 3 i o b u s 1 4 i o b u s 1 5 i o b u s 1 6 i o b u s 1 7 i o b u s 1 8 i o b u s 1 9 4 3 4 4 4 1 4 2 4 0 3 8 3 9 3 7 3 6 3 4 3 5 3 3 4 7 4 8 4 5 4 6 u s b 1 d p u s b 1 d m g n d c o r e u s b 2 d p u s b 2 d m v c c i o 3 . 3 v i o b u s 2 0 i o b u s 2 1 i o b u s 2 2 i o b u s 2 3 i o b u s 2 4 i o b u s 2 5 i o b u s 2 6 i o b u s 2 7 i o b u s 2 8 i o b u s 2 9 i o b u s 3 1 i o b u s 3 0 v c c i o 3 . 3 v i o b u s 3 2 i o b u s 3 3 g n d c o r e i o b u s 3 5 i o b u s 3 4 i o b u s 3 7 i o b u s 3 6 i o b u s 3 9 i o b u s 3 8 i o b u s 4 1 i o b u s 4 0 i o b u s 4 3 i o b u s 4 2 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 6 4 6 3 6 2 6 1 f t d i x x x x x x x x x x v n c 2 - 6 4 q 1 a y y w w 13 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 3.7 vnc2 schematic symbol 32 pi n figure 3 . 7 schematic s ymbol 32 p in v c c i o v c c i o v c c i o v r e g i n 1 8 1 7 8 u s b 1 d p u s b 1 d m r e s e t # p r o g # v r e g o u t n c u s b 2 d p u s b 2 d m 4 5 x t i n x t o u t v n c 2 3 2 p i n 7 1 0 9 2 1 2 0 2 8 2 2 1 3 3 n g n d g n d g d g n d 2 7 1 9 1 6 6 1 1 1 2 1 4 1 5 i o b u s 0 i o b u s 1 i o b u s 2 i o b u s 3 2 3 2 4 2 5 2 6 i o b u s 7 i o b u s 6 i o b u s 5 i o b u s 4 2 9 3 0 3 1 3 2 i o b u s 8 i o b u s 9 i o b u s 1 0 i o b u s 1 1 l p l g n d 1 v c c p l l i n 2 14 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 3.8 vnc2 schematic symbol 48 pin figure 3 . 8 schematic s ymbol 48 pin v c c i o v c c i o v c c i o 2 6 2 5 8 u s b 1 d p u s b 1 d m r e s e t # p r o g # v r e g o u t n c u s b 2 d p u s b 2 d m 4 5 x t i n x t o u t v n c 2 4 8 p i n 7 1 0 9 2 9 2 8 4 0 3 0 1 7 2 3 n g n d g n d g d g n d 3 9 2 7 2 4 6 1 1 1 2 1 3 1 4 i o b u s 0 i o b u s 1 i o b u s 2 i o b u s 3 1 5 1 6 1 8 1 9 i o b u s 7 i o b u s 6 i o b u s 5 i o b u s 4 2 0 2 1 2 2 2 3 i o b u s 8 i o b u s 9 i o b u s 1 0 i o b u s 1 1 3 1 3 2 3 3 3 4 i o b u s 1 5 i o b u s 1 4 i o b u s 1 3 i o b u s 1 2 3 5 3 6 3 7 3 8 i o b u s 1 6 i o b u s 1 7 i o b u s 1 8 i o b u s 1 9 4 1 4 2 4 3 4 4 i o b u s 2 3 i o b u s 2 2 i o b u s 2 1 i o b u s 2 0 4 5 4 6 4 7 i o b u s 2 4 i o b u s 2 5 i o b u s 2 6 i o b u s 2 7 4 8 l p l g n d 1 v r e g i n v c c p l l i n 15 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 3.9 vnc2 schematic symbol 64 pin figure 3 . 9 schematic s ymbol 64 pin v c c i o v c c i o v c c i o 3 4 3 3 8 u s b 1 d p u s b 1 d m r e s e t # p r o g # v r e g o u t n c u s b 2 d p u s b 2 d m 4 5 x t i n x t o u t v n c 2 6 4 p i n 7 1 0 9 3 7 3 6 5 4 3 8 2 1 2 3 n g n d g n d g d g n d 5 3 3 5 3 0 6 1 1 1 2 1 3 1 4 i o b u s 0 i o b u s 1 i o b u s 2 i o b u s 3 1 5 1 6 1 7 1 8 i o b u s 7 i o b u s 6 i o b u s 5 i o b u s 4 1 9 2 0 2 2 2 3 i o b u s 8 i o b u s 9 i o b u s 1 0 i o b u s 1 1 2 4 2 5 2 6 2 7 i o b u s 1 5 i o b u s 1 4 i o b u s 1 3 i o b u s 1 2 2 8 2 9 3 1 3 2 i o b u s 1 6 i o b u s 1 7 i o b u s 1 8 i o b u s 1 9 3 9 4 0 4 1 4 2 i o b u s 2 3 i o b u s 2 2 i o b u s 2 1 i o b u s 2 0 4 3 4 4 4 5 4 6 i o b u s 2 4 i o b u s 2 5 i o b u s 2 6 i o b u s 2 7 4 7 4 8 4 9 5 0 i o b u s 3 1 i o b u s 3 0 i o b u s 2 9 i o b u s 2 8 5 1 5 2 5 5 5 6 i o b u s 3 2 i o b u s 3 3 i o b u s 3 4 i o b u s 3 5 6 4 6 3 6 2 6 1 i o b u s 4 0 i o b u s 4 1 i o b u s 4 2 i o b u s 4 3 6 0 5 9 5 8 5 7 i o b u s 3 9 i o b u s 3 8 i o b u s 3 7 i o b u s 3 6 l p l g n d 1 v r e g i n v c c p l l i n 16 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 3.10 pin configuration usb and power pin no name type description 64 pin 48 pin 32 pin 33 25 17 usb1dp i/o usb host/slave port 1 - usb data signal plus with integrated pull - up/pull - down resistor . 34 26 18 usb1dm i/o usb host/slave port 1 - usb data signal minus with integrated pull - up/pull - down resistor . 36 28 20 usb2dp i/o usb host/slave port 2 - usb data signal plus with integrated pull - up/pull - down resistor . 37 29 21 usb2dm i/o usb host/slave port 2 - usb data signa l minus with integrated pull - up/pull - down resistor . table 3 . 1 usb interface group pin no name type description 64 pin 48 pin 32 pin 1, 30, 35, 53 1, 24, 27, 39 1, 16, 19, 27 gnd pwr device ground supply pins . 2 2 2 3.3v vregin pwr +3.3v supply to the regulator . 3 3 * 3 1.8 v vc c pll in pwr +1.8 v supply to the internal clock multiplier. this pin requires a 100nf decoupling capacitor . * 48 pin lqfp package only C this power input is internally connected to vreg_out. all other packages need this pin connected to a 1.8v power source. most common applications will connect this to vreg_out. 6 6 6 gnd pll pwr device analogue ground supply for internal clock multiplier . 7 7 * 7 vreg out output 1.8v output from regulator to device core * n/c on 48 pin lqfp package only. all other packages will typically need to connect pins 7 and 3. 21, 38, 54 17, 30, 40 13, 22 , 28 vc c io pwr +3.3v supply to the input / output . interface pins ( iobus) . leaving the vcci o unconnected will lead to unpredictable operation on the interface pins. table 3 . 2 power and ground 17 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 3.11 miscellaneous signal s pin no name type description 64 pin 48 pin 32 pin 4 4 4 xtin input input to 1 2mhz oscillator cell. connect 12mhz crystal across pins 4 and 5 . if driven by an external source, reference to 1.8v vcc pll in . 5 5 5 xtout output output from 12mhz oscillator cell. connect 12mhz crystal across pins 4 and 5 . no connect if xtin is drive n by an external source. 8 8 8 nc nc no c onnect (rev c) C (was test rev a, b) 9 9 10 reset# input c an be used by an external device to reset vnc2 . 10 10 9 prog# input asserting prog# on its own enables programming mode. table 3 . 3 miscellaneous signal group note 1 : # is used to indicate an active low signal. note 2: pin 9 and 10 are 5v safe inputs 18 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 3.12 pin configuration input / output vnc2 has multiple interfaces available for connectin g to external devices . these are uart, fifo , spi slave , spi master, gpio and pwm. the i nte rface i / o multiplexer is used to share the available i / o pins between each peripheral. vnc2 is configured with default settings for the i/o pins however they can be easily changed to suit the needs of a designer . this is explained in s ection 5 C i/o multiplexer. d ef ault configuration for each package type is shown in table 3 . 4 - defa ult i/o configuration . the signal names are also indicated for the vnc1l device as it is pin - compatible with the 48 pin lqfp vnc2 device. note: the default values of the pins listed in the following table are only available w hen the i/o mux is enabled. a b lank vnc2 chip defaults to all i/o pins as inputs. pin no name (vinc1 - l) 64 pin default 48 pin default 32 pin default type description 64 pin 48 pin 32 pin 11 11 11 IOBUS0 (bdbus0) debug_if debug_if debug_if i/o gpio 12 12 12 iobus1 (bdbus1) input pwm[1] gpio[ a 1] i/o gpio 13 13 14 iobus2 (bdbus2) input pwm[2] gpio[ a 2] i/o gpio 14 14 15 iobus3 (bdbus3) input pwm[3] gpio[ a 3] i/o gpio 15 15 23 iobus4 (bdbus4) fifo_data[0] spi_s0_clk uart_txd i/o gpio 16 16 24 iobus5 (bdbus5) fifo_data[1] spi _s0_mosi uart_rxd i/o gpio 17 18 25 iobus6 (bdbus6) fifo_data[2] spi_s0_miso uart_rts# i/o gpio 18 19 26 iobus7 (bdbus7) fifo_data[3] spi_s0 _ss# uart_cts# i/o gpio 19 20 29 iobus8 (bc bus0) fifo_data[4] spi_m_clk spi_s0_clk i/o gpio 20 21 30 iobus9 (bc bus1) fifo_data[5] spi_m_mosi spi_s0_mosi i/o gpio 22 22 31 iobus10 (bc bus2) fifo_data[6] spi_m_miso spi_s0_miso i/o gpio 23 23 32 iobus11 (bc bus3) fifo_data[7] spi_m_s s _0 # spi_s0 _ss# i/o gpio 24 31 - iobus12 (adbus0) fifo_rxf# uart_txd i/o gpio 25 32 - iobus13 (adbus1) fifo_txe# uart_rxd i/o gpio 26 33 - iobus14 (adbus2) fifo_rd# uart_rts# i/o gpio 19 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 pin no name (vinc1 - l) 64 pin default 48 pin default 32 pin default type description 64 pin 48 pin 32 pin 27 34 - iobus15 (adbus3) fifo_wr# uart_cts# i/o gpio 28 35 - iobus16 (adbus4) fifo_oe# uart_dtr# i/o gpio 29 36 - iobus17 (adbus5) input uart_dsr# i/o gpio 31 37 - iobus18 (adbus6) input uart_dcd# i/o gpio 32 38 - iobus19 (adbus7) input uart_ri# i/o gpio 39 41 - iobus20 (ac bus0) uart_txd uart_tx_active i/o gpio 40 42 - iobus21 (ac bus1) uart_rxd gpio[ a 5] i/o gpio 41 43 - iobus22 (ac bus2) uar t_rts# gpio[ a 6] i/o gpio 42 44 - iobus23 (ac bus3) uart_cts# gpio[ a 7] i/o gpio 43 45 - iobus24 (ac bus4) uart_dtr# gpio[ a 0] i/o gpio 44 46 - iobus25 (ac bus5) uart_dsr# gpio[ a 1] i/o gpio 45 47 - iobus26 (ac bus6) uart_dcd# gpio[ a 2] i/o gpio 46 48 - i obus27 (ac bus7) uart_ri# gpio[ a 3] i/o gpio 47 - - iobus28 uart_tx_active i/o gpio 48 - - iobus29 input i/o gpio 49 - - iobus30 input i/o gpio 50 - - iobus31 input i/o gpio 51 - - iobus32 spi_s0_clk i/o gpio 52 - - iobus33 spi_s0_mosi i/o gpio 55 - - iobus34 spi_s0_miso i/o gpio 56 - - iobus35 spi_s0 _ss# i/o gpio 57 - - iobus36 spi_s1_clk i/o gpio 20 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 pin no name (vinc1 - l) 64 pin default 48 pin default 32 pin default type description 64 pin 48 pin 32 pin 58 - - iobus37 spi_s1_mosi i/o gpio 59 - - iobus38 spi_s1_miso i/o gpio 60 - - iobus39 spi_s1 _ss# i/o gpio 61 - - iobus40 spi _m_clk i/o gpio 62 - - iobus41 spi_m_mosi i/o gpio 63 - - iobus42 spi_m_miso i/o gpio 64 - - iobus43 spi_m _s s _0 # i/o gpio table 3 . 4 default i/o configuration note: all gpio are 5v safe inputs 21 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 4 f unction description vnc2 is the second of ftdi s vinculum family of embedded usb host controller integrated circuit devices. vnc2 can encapsulate certain usb device classes by handling the usb host interface and data transfer functions using the in - built e m cu and embedded flash memory. when interfacing to mass storage devices, such as usb flash drives, vnc2 transparently handles the fat file s tructure using a simple to implement command set. vnc2 provides a cost effective solution for introducing usb host ca pability into products that previously did not have the hardware resources to do so. vnc2 has an associated software development tool suite to allow users to create customised firmware . 4.1 key features vnc2 is a programmable soc device with a powerful embedd ed microprocesso r core and dual usb int erfaces , large ram and flash capacity and the ability to develop and customise firmware using the vnc2 t oolchain. vnc2 has an enhanced featu re list over and above vnc1l ; however the 48 pin lqfp package is backwa rd com patible with the vnc1l . 4.2 functional block descriptions the following paragraphs de scribe each function within vnc2 . please refer to the block diagram shown in figure 2 . 1 4.2.1 embedded cpu the p rocessor core is based on ftdi s proprietary 16 - bit embedded mcu architecture. the e mcu has a harvard architecture with separate code and data space. 4.2.2 flash module vnc2 has 256k bytes ( 128k x 16 - bits) of embedded flash (e - flash) memory. no special programming voltages are necess ary for programming the on - board e - flash as these are provided internally on - chip. 4.2.3 flash programming module the purpose of the flash programmer module is to perform all necessary operations for programming the flash, from general usage to first power o n sequencing. this block is responsible for handling device f irmware upgrade s which can be accessed by the d ebugger interface, a usb cable or flash drive interface. 22 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 4.2.4 input / output multiplexer module vnc2 peripheral interfaces are uart, spi slave 0, spi slav e1, spi master, fifo - asynchronous , fifo - synchronous, gpio, debug interface and pwm. the i/o multiplexer allows the designer to select which peripherals are connected to the device i/o pins. the selectable peripheral interfaces are only limited by the num ber of i/o pins available. all peripheral s are available across the package range except synchronous fifo mode which cannot be selected on 32 pin packages. the available configurable i/o pins per package are as follows: ? 32 pin package C 12 i/o pins ? 48 pin package C 28 i/o pins ? 64 pin package C 44 i/o pins table 4 . 1 lists the peripherals which can be multiplexed to i/o and the maximum number of pins required for each one . the designer can choose any mix of periphe ral configurations as long as they are within the specific package i/o pin count . depending on the design not all 9 uart pins need to be configured . similarly the gipo peripheral does not need all pins configured. e.g. the 48 pin package has 28 i/o pins w hich could be configured as uart C 9 pins, spi master C 5 pins, fifo asynchronous C 12 pins and gpio C 2 pins. this makes a total of 28 pins. please refer to section 5 for a detailed description of the i/o multi plexer. peripherals maximum pins required uart 9 spi slave 0 4 spi slave 1 4 spi master 5 fifo asynchronous 12 fifo synchronous 14 gpio 4 0 debug 1 pwm 8 table 4 . 1 - peripheral pin requirements 23 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 4.2.5 peripheral dma m odule s 0, 1, 2 & 3 the peripheral dma has the capability to transfer data to and from an i/o device. the cpu can offload the transfer of data between the processor and the peripheral freeing the cpu to execute other instructions. the dma module collect s or transmits data from memory to an i / o address space; it is also capable of copying data in memory and transferring it to another location. the dma is not accessible by the user as it automatically controlled by the cpu. 4.2.6 ram module the ram module consist s of 16k bytes on - chip ( 4k x 32 - bits) data memory. the ram is byte addressable. 4.2.7 peripheral interface modules vnc2 has nine peripheral interface modules. full descriptions of each module are described in section 6 . ? debugger interface ? uart ? pwm ? fifo ? spi master ? spi slave 0 & 1 ? gpio - general purpose i/o pins ? general purpose timers 4.2.8 usb transceivers 0 and 1 t wo usb transceiver cells provide the physical usb device interface supporting usb 1.1 and usb 2.0 standards. low - speed and full - speed usb data rates are supported. each output driver provide s + 3.3v level slew rate control signalling, whilst a differential receiver and two single ended receivers provide usb data in , se 0 and usb reset condition detecti on. these cells also include integrated internal usb pull - up or pull - down resistors as required for host or slave mode. 4.2.9 usb host / device controllers t hese blocks handle the parallel - to - serial and serial - to - parallel conversion of the usb p hysical l ayer . this includ es bit stuffing , crc generation, usb frame generation and protocol error checking. the host / device controller is autonomous and therefore requires limited load from the cpu. 4.2.10 12mhz oscillator the 12mhz oscillator cell generates a 12mhz r eference clock input to the clock multiplier pll from an external 12mhz crystal. the external crystal is connected across pin 4 C xtin and pin 5 C xtout in the configuration shown in figure 10 . 1 . 4.2.11 power saving mode s and standby mode. vnc2 can be set to operate in three frequencies allowing the user to select a slo wer speed to reduce power consumption . three operating frequencies available are 12mhz, 24mhz and normal operation of 48mhz. these operating modes can be configured using the rtos. full details are available in the rtos manual available from the ftdi website . when a particular peripheral is not used, it is powered down internally thus saving power. standby mode is av ailable under firmware control, this mode puts the vnc2 in a state with no clocks running or system blocks powered. the device will wake up out of this mode by toggling any of the following signals : usb0/1 dp or dm , spi slave 0 select ( spi_s0_ss #) , spi sla ve 1select ( spi_s1_ss # ) or uart ring indicator ( uart_ri# ). 24 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 5 i/o multiplexer ftdi devices typically have multiple interfaces available to communicate with external devices. vnc2 has uart, spi slave 0, spi slave1, spi master, fifo, gpio, and pwm peripherals. t he available packages for vnc2 provide any of these interfaces to be active on the available pins through the use of an i/o multiplexer. table 5 . 1 lists the signals available f or each peripheral . table 5 . 2 to 12 explain the use of the i/o multiplexer. multiplexers are used to connect the vnc2 peripherals to the external iobus pins. this enables the designer to select which iobus pins he wishes to map a particular peripheral to. peripheral signals are allocated to one of four groups, which connect to the i/o multiplexer. each i/o peripheral signal can connect to one out of every four external iobus pins. the iobus pin that a peripheral signal can connect to is dictated by the peripheral signals group. for example, if a peripheral signal is allocated to group 0 then it can connect to IOBUS0, iobus4, iobus8, and iobus12 and so on. if a peripheral signal is allocated to group 1 then it can connect to iobus1, iobus5, iobus9, and iobus13 and so on. figure 5 . 1 details the i/o multiplexer concept, where, for example, a white peripheral signal can connect to any white iobus pin; a green peripheral signal can connect to a green iobus pin. figure 5 . 2 , figure 5 . 3 and figure 5 . 4 give examples of connecting peripheral signals to differing iobus pins. the io multiplexer also provides the following features: ? ability to configure an i/o pad as an input, output or bidirectional pad. ? at power on reset, all pins are set as inputs by default. whenever the i/o mux is enabled the pins are configured as their default values listed ta ble 6 with in section 3. 12 . note: it is recommended not to reassign the debug interface signal (debug_if) from its default setting of IOBUS0 (pin 11 on all packages). this assumes that the debug pin is required in the application design, if not; pin 11 can be assigned to any other group 0 signal. an application (iomux) within the rtos is available to aid with pin configuration, section 5.2 has more details. further details of the io m ultiplexer are available within application note an_139 vinculum - ii io mux explained . 25 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 figure 5 . 1 iobus to group r elationship - 64 p in i o b u s 0 i o b u s 1 i o b u s 2 i o b u s 3 i o b u s 4 i o b u s 5 i o b u s 6 i o b u s 7 i o b u s 8 i o b u s 9 i o b u s 1 0 i o b u s 1 1 i o b u s 1 2 i o b u s 1 3 i o b u s 1 4 i o b u s 1 5 i o b u s 1 6 i o b u s 1 7 i o b u s 1 8 i o b u s 1 9 i o b u s 2 0 i o b u s 2 1 i o b u s 4 3 u a r t _ t x d u a r t _ r x d u a r t _ r t s # u a r t _ c t s # u a r t _ d t r # u a r t _ d s r # u a r t _ d c d # u a r t _ r i # u a r t _ t x _ a c t i v e p e r i p h e r a l p i n i o b u s p i n g r o u p 0 a l l o c a t e d p i n g r o u p 1 a l l o c a t e d p i n g r o u p 2 a l l o c a t e d p i n g r o u p 3 a l l o c a t e d p i n k e y : 26 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 figure 5 . 2 details the uart, spi slave0 and spi master connecting to iobus pins: figure 5 . 2 iobus to uart, spi slave0 and spi master example i o b u s 0 i o b u s 1 i o b u s 2 i o b u s 3 i o b u s 4 i o b u s 5 i o b u s 6 i o b u s 7 i o b u s 8 i o b u s 9 i o b u s 1 0 i o b u s 1 1 i o b u s 1 2 i o b u s 1 3 i o b u s 1 4 i o b u s 1 5 i o b u s 1 6 i o b u s 1 7 i o b u s 1 8 i o b u s 1 9 i o b u s 2 0 i o b u s 2 1 i o b u s 2 2 i o b u s 2 3 i o b u s 2 4 i o b u s 2 5 i o b u s 2 6 i o b u s 2 7 i o b u s 2 8 i o b u s 2 9 i o b u s 3 0 i o b u s 3 1 i o b u s 4 3 u a r t _ t x d u a r t _ r x d u a r t _ r t s # u a r t _ c t s # u a r t _ d t r # u a r t _ d s r # u a r t _ d c d # u a r t _ r i # u a r t _ t x _ a c t i v e s p i _ s 0 _ c l k s p i _ s 0 _ m o s i s p i _ s 0 _ m i s o s p i _ s 0 _ s s # s p i _ s 1 _ c l k s p i _ s 1 _ m o s i s p i _ s 1 _ m i s o s p i _ s 1 _ s s # s p i _ m _ c l k s p i _ m _ m o s i s p i _ m _ m i s o s p i _ m _ s s _ 0 # s p i _ m _ s s _ 1 # p e r i p h e r a l p i n i o b u s p i n g p i o [ a 0 ] g p i o [ a 1 ] g p i o [ a 2 ] g p i o [ a 3 ] g p i o [ a 4 ] g p i o [ a 5 ] g p i o [ a 6 ] g p i o [ a 7 ] g p i o [ e 7 ] 27 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 figure 5 . 3 expands upon figure 5 . 2 by moving the uart, spi slave0 and spi master signals to differ ent iobus positions. the purpose of this diagram to highlight peripherals connected to differing iobus positions. figure 5 . 3 iobus to uart , spi slave0 and spi master second example i o b u s 0 i o b u s 1 i o b u s 2 i o b u s 3 i o b u s 4 i o b u s 5 i o b u s 6 i o b u s 7 i o b u s 8 i o b u s 9 i o b u s 1 0 i o b u s 1 1 i o b u s 1 2 i o b u s 1 3 i o b u s 1 4 i o b u s 1 5 i o b u s 1 6 i o b u s 1 7 i o b u s 1 8 i o b u s 1 9 i o b u s 2 0 i o b u s 2 1 i o b u s 2 2 i o b u s 2 3 i o b u s 2 4 i o b u s 2 5 i o b u s 2 6 i o b u s 2 7 i o b u s 2 8 i o b u s 2 9 i o b u s 3 0 i o b u s 3 1 i o b u s 4 3 u a r t _ t x d u a r t _ r x d u a r t _ r t s # u a r t _ c t s # u a r t _ d t r # u a r t _ d s r # u a r t _ d c d # u a r t _ r i # u a r t _ t x _ a c t i v e s p i _ s 0 _ c l k s p i _ s 0 _ m o s i s p i _ s 0 _ m i s o s p i _ s 0 _ s s # s p i _ s 1 _ c l k s p i _ s 1 _ m o s i s p i _ s 1 _ m i s o s p i _ s 1 _ s s # s p i _ m _ c l k s p i _ m _ m o s i s p i _ m _ m i s o s p i _ m _ s s _ 0 # s p i _ m _ s s _ 1 # p e r i p h e r a l p i n i o b u s p i n g p i o [ a 0 ] g p i o [ a 1 ] g p i o [ a 2 ] g p i o [ a 3 ] g p i o [ a 4 ] g p i o [ a 5 ] g p i o [ a 6 ] g p i o [ a 7 ] g p i o [ e 7 ] 28 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 with reference to figure 5 . 3 , it can be seen that iobus9 - 11 and iobus16 - 19 were unused. figure 5 . 4 expands upon the previ ous two figures to detail a fully occupied iobus, up to and including iobus19. the gaps at iobus9 - 11 have been filed with 3 gpio pins, the gaps at iobus16 - 19 have been filled with the second spi slave and a further 3 iobus pins (17 - 19) have been allocated to 3 gpio pins. note that gpio pins a 0 and a 4 are unused as a sufficient gap wasn't available. figure 5 . 4 iobus to uart, spi slave0 and spi master third example i o b u s 0 i o b u s 1 i o b u s 2 i o b u s 3 i o b u s 4 i o b u s 5 i o b u s 6 i o b u s 7 i o b u s 8 i o b u s 9 i o b u s 1 0 i o b u s 1 1 i o b u s 1 2 i o b u s 1 3 i o b u s 1 4 i o b u s 1 5 i o b u s 1 6 i o b u s 1 7 i o b u s 1 8 i o b u s 1 9 i o b u s 2 0 i o b u s 2 1 i o b u s 2 2 i o b u s 2 3 i o b u s 2 4 i o b u s 2 5 i o b u s 2 6 i o b u s 2 7 i o b u s 2 8 i o b u s 2 9 i o b u s 3 0 i o b u s 3 1 i o b u s 4 3 u a r t _ t x d u a r t _ r x d u a r t _ r t s # u a r t _ c t s # u a r t _ d t r # u a r t _ d s r # u a r t _ d c d # u a r t _ r i # u a r t _ t x _ a c t i v e s p i _ s 0 _ c l k s p i _ s 0 _ m o s i s p i _ s 0 _ m i s o s p i _ s 0 _ s s # s p i _ s 1 _ c l k s p i _ s 1 _ m o s i s p i _ s 1 _ m i s o s p i _ s 1 _ s s # s p i _ m _ c l k s p i _ m _ m o s i s p i _ m _ m i s o s p i _ m _ s s _ 0 # s p i _ m _ s s _ 1 # g p i o [ a 0 ] g p i o [ a 1 ] g p i o [ a 2 ] g p i o [ a 3 ] g p i o [ a 4 ] g p i o [ a 5 ] g p i o [ a 6 ] g p i o [ a 7 ] g p i o [ e 7 ] p e r i p h e r a l p i n i o b u s p i n 29 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 5.1 i/o peripherals signal names peripheral signal name outputs inputs description debugger debug_if 1 1 debugger interface uart uart_txd 1 0 transmit a synchronous data output uart_rts # 1 0 request to send control o utput uart_dtr # 1 0 data acknowledge (data terminal re ady control) o utput uart_tx_active 1 0 enable transmit d ata for rs485 designs uart_rxd 0 1 receive asynchronous data input uart_cts # 0 1 c lear to send control i nput uart_dsr # 0 1 data request (data set ready control) i nput uart_ri# 0 1 ring indic ator control i nput uart_dcd# 0 1 data carrier detect control i nput fifo fifo_data 8 8 fifo data bus fifo_txe# 1 0 when high, do not write data into the fifo. when low, data can be written into the fifo by strobing wr high, then low. fifo_rxf# 1 0 wh en high, do not read data from the fifo. when low, there is data available in the fifo which can be read by strobing rd# low, then high. fifo_wr# 0 1 writes the data byte on the d0...d7 pins into the transmit fifo buffer when wr goes from high to low. fifo_rd# 0 1 enables the current fifo data byte on d0...d7 when low. fetches the next fifo data byte (if available) from the receive fifo buffer when rd# goes from high to low fifo_oe# 0 1 fifo output enable C synchronous fifo only fifo_clkout 0 1 fifo clock out C synchronous fifo only gpio gpio 4 0 4 0 general purpose i/o spi slave 0 spi_s0_clk 0 1 spi c lock input C slave 0 spi_s0 _ss# 0 1 spi chip select i nput C slave 0 spi_s0_mosi 1 1 spi master o ut s erial i n C slave 0 spi_s0_miso 1 0 spi m aster in slave o ut C slave 0 spi slave 1 spi_s1_clk 0 1 spi c lock input C slave 1 spi_s1 _ss# 0 1 spi chip select i nput C slave 1 spi_s1_mosi 1 1 master out slave i n C slave 1 spi_s1_miso 1 0 master in s lave out C slave 1 spi master spi_m_clk 1 0 spi clo ck input C master spi_m_mosi 1 1 master out slave in - master spi_m_miso 0 1 master in slave out - master spi_m_ss_0# 1 0 active low slave select 0 from master to slave 0 spi_m_ss_1# 1 0 active low slave select 1 from master to slave 1 pwm pwm 8 0 pulse width modulation table 5 . 1 i / o peripherals signal names note: # is used to indicate an active low signal. 30 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 5.2 i/o mu ltiplexer configuration the vnc2 i/o multiplexer allows signals to be routed to d ifferent pins on the device . to simplify the routing of signals, the vnc2 rtos provides an utility ( iomux ) to configure the i/o multiplexer as the designer requires. the iomux is fully integrated into the vnc2 ide (integrated development environment) whic h is available to download : vinculum - ii toolchain . a screenshot of the iomux utility is shown in figure 5.5 below. the iomux utility user guide is available to download: vinculum - ii io_mux configuration utility user guide the following tables provide a lookup guide to determine what signals ar e available and the list of pins that can be used: ? table 5 . 2 gr oup 0 ? table 5 . 3 gr oup 1 ? table 5 . 4 group 2 ? table 5 . 5 group 3 each vnc2 has a default state of iobus signals following a hard reset. t he number of i/o pins available is determined by the package size: ? package 32pin (lqfp & qfn) - twelve i/o pins C IOBUS0 to iobus11 ? package 48pi n (lqfp & qfn) - twenty eight i/o pins C IOBUS0 to iobus27 ? package 64pin (lqfp & qfn) - forty - four i/o pins C IOBUS0 to iobus43 section 3.12 shows the default signal settings for all three package sizes. figure 5 . 5 vnc2 toolchain app wizard showing iomux configuration 31 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 5.3 i/o mux group 0 available input signals available output signals 64 pin package available pins 48 pin package available pins 32 pin package availab le pins debug_if fifo_data[0] fifo_data[4] fifo_oe # spi_s0_clk spi_s1_clk gpio[ a 0] gpio[ a 4] gpio[ b 0 ] gpio[ b 4 ] gpio[ c 0 ] gpio[ c 4 ] gpio[ d 0 ] gpio[ d 4 ] gpio[ e 0 ] gpio[ e 4 ] debug_if uart_txd uart_dtr # uart_tx_active fifo_data[0] fifo_data[4] fifo_rxf # pwm[0] pwm[ 4] spi_m_clk spi_m _s s_1# gpio[a0] gpio[a4] gpio[b0] gpio[b4] gpio[c 0] gpio[c 4] gpio[d0] gpio[d4] gpio[e0] gpio[e4] 11, 15, 19, 24, 28, 39, 43, 47, 51, 57, 61 11, 15, 20, 31, 35, 41, 45 11, 23 29 table 5 . 2 gr oup 0 table 5 . 2 - input and output signals that are available for all the iobus pins that are in group 0. for example i f using the 48 pin package dev ice this would allow pins 11, 15, 20, 31, 35, 41 and 45 to be co nfigured as either an input signal (listed in the first column) or a output signal (listed in the second column). 32 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 5.4 i/o mux group 1 available input signals available output signals 64 pin package available pins 48 pin package available pins 32 pin package available pins uart_rxd uart_dsr # fifo_data[1] fifo_data[5] spi_s0_mosi spi_s1_mosi gpio[ a 1] gpio[ a 5] gpio[ b 1 ] gpio[ b 5 ] gpio[ c 1 ] gpio[ c 5 ] gpio[ d 1 ] gpio[ d 5 ] gpio[ e 1 ] gpio[ e 5 ] fifo_data[1] fifo_data[5] fifo_txe # pwm[1] pwm[5] spi_s0_mosi spi_s1_mos i spi_m_mosi fifo_clkout gpio[a1] gpio[a5] gpio[b1] gpio[b5] gpio[c 1] gpio[c 5] gpio[d1] gpio[d5] gpio[e1] gpio[e5] 12, 16, 20, 25, 29, 40, 44, 48, 52, 58, 62 12,16, 21, 32, 36, 42, 46 12, 24, 30 table 5 . 3 gr oup 1 table 5 . 3 - input and output signals that are available for all the iobus pins that are in group 1. for example i f using the 64 pin package dev ice this would allow pins 12, 16, 20, 25, 29, 40, 44, 48, 52, 58 and 62 to be configured as either an input signal (listed in the first column) or a output signal (listed in the second column). 33 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 5.5 i/o mux group 2 available input signals available output signals 64 pin package available pins 48 pin package available pins 32 pin package available pins uart_dcd# fifo_data[2] fifo_data[6] fifo_rd # spi_m_miso gpio[ a 2] gpio[ a 6] gpio[ b 2 ] gpio[ b 6 ] gpio[ c 2 ] gpio[ c 6 ] gpio[ d 2 ] gpio[ d 6 ] gpio[ e 2 ] gpio[ e 6 ] uart_rts # fifo_data[2] fifo_data[6] pwm[2] pwm[6] spi_s0_miso s pi_s1_miso gpio[a2] gpio[a6] gpio[b2] gpio[b6] gpio[c 2] gpio[c 6] gpio[d2] gpio[d6] gpio[e2] gpio[e6] 13, 17, 22, 26, 31, 41, 45, 49, 55, 59, 63 13, 18, 22, 33, 37, 43, 47 14, 25, 31 table 5 . 4 group 2 table 5 . 4 - input and output signals that are available for all the iobus pins that are in group 2. for example i f using the 32 pin package dev ice this would allow pins 14, 25 and 31 to be configured as either an input signal (listed in the first column) or a output signal (listed in the second column). 34 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 5.6 i/o mux group 3 available input signals available output signals 64 pin package available pins 48 pin package available pins 32 pin package available pin s uart_cts # uart_ri# fifo_data[3] fifo_data[7] fifo_wr # spi_s0 _ss# spi_s1 _ss# gpio[ a 3] gpio[ a 7] gpio[ b 3 ] gpio[ b 7 ] gpio[ c 3 ] gpio[ c 7 ] gpio[ d 3 ] gpio[ d 7 ] gpio[ e 3 ] gpio[ e 7 ] fifo_data[3] fifo_data[7] pwm[3] pwm[7] spi_m _s s_0# gpio[a3] gpio[a7] gpio[b3] gpio[b7] gpio[c 3] gpio[c 7] gpio[d3] gpio[d7] gpio[e3] gpio[e7] 14, 18, 23, 27, 32, 42, 46, 50, 56, 60, 64 14, 19, 23, 34, 38, 44, 48 15, 26, 32 table 5 . 5 group 3 table 5 . 5 - input and output signals that are available for all the iobus pins that are in group 3. for example i f you using the 48 pin package dev ice this would allow pins 14, 19, 23, 34, 38, 44 and 48 to be configured as either an input signal ( listed in the first column ) or a output signal ( listed in the second column ) . 35 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 5.7 i/o mux interface c onfiguration example this example shows how to set a uart interface on the vnc2 64 pin package. the uart is made up of two output signals ( uart_txd and uart_rts # ) and two input signals (uart_rxd and uart_cts # ). for pcb design it is best to have the four p ins of the uart interface adjacent to each other. this can be achieved easily since the four signals are members of each different groups . figure 5 . 1 clearly shows that the four groups are adjacent to each other. so the four adjacent pins can be used for the uart interface as long as they are selected one from each of the four groups. tables 9, 10, 11 & 12 can now be used to select where the uart interface can be placed. figure 5 . 6 shows the four uart signal selected on pins 11, 12, 13 & 14 however they could have been selected on any of the other four pins highlighted in blue dashed l ines . figure 5 . 6 uart example 64 pin v c c i o v c c i o v c c i o v c c p v c c 3 4 3 3 8 u s b 1 d p u s b 1 d m r e s e t # p r o g # v r e g o u t n c u s b 2 d p u s b 2 d m 4 5 x t i n x t o u t v n c 2 6 4 p i n 7 1 0 9 3 7 3 6 5 4 3 8 2 1 2 3 n g n d g n d g d g n d 5 3 3 5 3 0 6 1 1 1 2 1 3 1 4 i o b u s 0 i o b u s 1 i o b u s 2 i o b u s 3 1 5 1 6 1 7 1 8 i o b u s 7 i o b u s 6 i o b u s 5 i o b u s 4 1 9 2 0 2 2 2 3 i o b u s 8 i o b u s 9 i o b u s 1 0 i o b u s 1 1 2 4 2 5 2 6 2 7 i o b u s 1 5 i o b u s 1 4 i o b u s 1 3 i o b u s 1 2 2 8 2 9 3 1 3 2 i o b u s 1 6 i o b u s 1 7 i o b u s 1 8 i o b u s 1 9 3 9 4 0 4 1 4 2 i o b u s 2 3 i o b u s 2 2 i o b u s 2 1 i o b u s 2 0 4 3 4 4 4 5 4 6 i o b u s 2 4 i o b u s 2 5 i o b u s 2 6 i o b u s 2 7 4 7 4 8 4 9 5 0 i o b u s 3 1 i o b u s 3 0 i o b u s 2 9 i o b u s 2 8 5 1 5 2 5 5 5 6 i o b u s 3 2 i o b u s 3 3 i o b u s 3 4 i o b u s 3 5 6 4 6 3 6 2 6 1 i o b u s 4 0 i o b u s 4 1 i o b u s 4 2 i o b u s 4 3 6 0 5 9 5 8 5 7 i o b u s 3 9 i o b u s 3 8 i o b u s 3 7 i o b u s 3 6 l p l g n d 1 l l u a r t _ t x d C g r o u p 0 u a r t _ c t s # C g r o u p 3 u a r t _ r t s # C g r o u p 2 u a r t _ r x d C g r o u p 1 36 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 6 peripheral interfaces in addition to the two usb host and slave blocks, vnc2 contains the following peripheral interfaces: ? universal asynch ronous receiver transmitter (uart) ? two serial peripheral interface (spi) slaves ? spi master ? debugger interface ? parallel fifo interface (245 mode and synchronous fifo mode ) ? general purpose timers ? eight pulse width modulation blocks (pwm) ? general purpose inpu t output (gpio) the following sections describe each peripheral in detail. 6.1 uart interface when the data and control bus are configured in uart mode, the interface implements a standard asynchronous serial uart port with flow control , for example rs232/42 2/485 . the uart can support b aud rates from 183 baud to 6 m baud . the maximum uart speed is determined by the cpu speed/ 8 . the cpu can be run at three frequencies , therefore the following maximum rates apply: cpu frequency maximum uart speed 48 mhz 6 mba ud 24 mhz 3 mbaud 12 mhz 1.5 mbaud data transfer uses nrz (non - return to zer o) data format consisting of 1 s tart bit, 7 or 8 data bits, an optio nal parity bit, and one or two s top bits. when transmitting the data bits, the least significant bit is tra nsmitted first. transmit and receive waveforms are illustrated in figure 6 . 1 and figure 6 . 2 : figure 6 . 1 uart receive wavef orm figure 6 . 2 uart transmit waveform baud rate (default =9600 baud) , flow control settings (default = rts/cts) , number of data bits (default=8) , parity (default is no parity) and number of s top bits (defa ult=1) are all configurable using the firmware command interface. please refer to http://www.ftdichip.com . uart_tx_active is transmit enable, this output may be used in rs485 designs to control the transmit of the li ne driver. 37 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 6.1.1 uart mode signal descriptions 64 pin package available pins 48 pin package available pins 32 pin package available pins name type description 11, 15, 19, 24, 28, 39, 43, 47, 51, 57, 61 11, 15, 20, 31, 35, 41, 45 11, 23 29 uart_txd output transm it asynchronous data output 12, 16, 20, 25, 29, 40, 44, 48, 52, 58, 62 12,16, 21, 32, 36, 42, 46 12, 24, 30 uart_rxd input receive asynchronous data input 13, 17, 22, 26, 31, 41, 45, 49, 55, 59, 63 13, 18, 22, 33, 37, 43, 47 14, 25, 31 uart_rts # output request to send c ontrol o utput 14, 18, 23, 27, 32, 42, 46, 50, 56, 60, 64 14, 19, 23, 34, 38, 44, 48 15, 26, 32 uart_cts # input c lear to send c o ntrol i nput 11, 15, 19, 24, 28, 39, 43, 47, 51, 57, 61 11, 15, 20, 31, 35, 41, 45 11, 23 29 uart_dtr # output d ata acknowledge (data terminal ready control) o utput 13, 17, 22, 26, 31, 41, 45, 49, 55, 59, 63 13, 18, 22, 33, 37, 43, 47 14, 25, 31 uart_dcd# input data carrier detect control i nput 38 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 64 pin package available pins 48 pin package available pins 32 pin package available pins name type description 14, 18, 23, 27, 32, 42, 46, 50, 56, 60, 64 14, 19, 23, 34, 38, 44, 48 15, 26, 32 uart_ri# input ring indicator is used to wake vnc2 depending on firmware 11, 15, 19, 24, 28, 39, 43, 47, 51, 57, 61 11, 15, 20, 31, 35, 41, 45 11, 23 29 uart_tx_active output enable transmit d ata for rs485 designs . t his signal may be used to s ignal that a transmit operation is in progress. the uart_tx_active signal will be set high one bit - time before data is transmitted and return low one bit time after the last bit of a data frame has been transmitted. table 6 . 1 data and control bus signal mode options C uart interface the uart signals can be programmed to a choice of i/o pins depending on the package size. table 6 . 1 details the available pins for each of the uart signals. further details on the configuration of input and output signals are available in s ection 5 - i/o multiplexer . 39 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 6.2 serial peripheral interface C spi modes the serial peripheral interface bus is a n industry standard communications interface. devices communicate in master / slave mode, with the master initiating the data transfer. vnc2 has one master module and two slave modules. each spi slave module has four si gnals C clock, slave select, mosi (ma ster out C slave in) and miso (master in C slave out) . the spi master has the same four signals as the slave modules but with one additional signal because it requires a slave select for the second slave module. table 6 . 2 lists how the signals are named in each module. the spi master clock can operate up to one half of the cpu system clock depending on what power mode the device is set to: ? normal power mode 48 mhz would set the spi maximum clock to 2 4 m h z ? low power mo de 24 mhz would set the spi maximum clock to 12 m h z ? lowest power mode 12mhz would set the spi maximum clock to 6 h mz module signal name type description spi slave 0 spi_s0_clk input c lock input C slave 0 spi_s0 _ss# input active low c hip select input C sla ve 0 spi_s0_mosi input master out serial in C slave 0 spi_s0_miso output master in slave out C slave 0 spi slave 1 spi_s1_clk input c lock input C slave 1 spi_s1 _ss# input active low c hip select input C slave 1 spi_s1_mosi input master out slave in C slave 1 spi_s1_miso output master in slave out C slave 1 spi master spi_m_clk out put c lock out put C master spi_m_mosi output master out slave in - master spi_m_miso input master in slave out - master spi_m _s s_0# output active low slave select 0 from master to slave 0 spi_m _s s_1# output active low slave select 1 from master to slave 1 table 6 . 2 spi signal names the spi slave protocol by default does not support any form of handshaking . ftdi have a dded extra modes to support handshaking, faster throughput of data and reduced pin c ount. there are 5 modes ( table 15 ) of operation in the vnc2 spi slave. ? full duplex C section 0 ? half duplex, 4 pin - section 6.3.3 ? half duplex, 3 pin - section 6.3.4 ? unmanaged - section 6.3.5 ? vnc1l legacy mode C section 6.3.6 40 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 mode pins word size handshaking speed comments vnc 1l 4 12 yes read 66% write 66% legacy mode full duplex 4 8 yes read 50% write 100% half duplex 4 pin 4 8 yes read 100% write 100% mosi becomes bi - directional half duplex 3 pin 3 8 yes read 50% write 50% mosi becomes bi - directional unman aged 4 8 no read 100% write 100% table 6 . 3 - spi slave speeds vnc2 spi master is described in section 6.4.1 spi master signal descriptions. table 6 . 5 shows the spi master signals and the available pins that they can be mapped to depending on the package size. further deta ils on the configuration of input and output signals are available in s ection 5 - i/o multiplexer . 6.2.1 spi clock phase modes spi interface has 4 unique modes of clock phase (cpha) and clock polarity (cpol), known as m ode 0, mode 1, mode 2 and mode 3. table 6 . 4 summarizes these modes and available interface and figure 6 . 3 is the function timing diagram. for cpol = 0, the base (inactive) level of sclk is 0. in this mode: ? when cpha = 0, data is clocked in on the rising edge of sclk, and data is clocked out on the falling edge of sclk. ? when cpha = 1, data is clocked in on the falling edge of sclk, and data is clocked out on the rising edge of sclk for cpol =1, the base (inactive) level of sclk is 1. in this mode: ? when cpha = 0, data v in on the falling edge of sclk, and data is clocked out on the rising edge of sclk ? when cpha =1, data is clocked in on the rising edge of sclk, and data is clocked out on the falling edge of sclk. mode cpol cpha full duplex half duplex 4 pin half duplex 3 pin unmanaged vnc1l legacy 0 0 0 n n n y n 1 0 1 y y y y n 2 1 0 n n n y n 3 1 1 y y y y n table 6 . 4 - clock phase/polarity modes 41 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 figure 6 . 3 - spi cpol cpha f unc tion 6.3 serial peripheral interface C slave figure 6 . 4 spi slave blo ck diagram vnc2 has two spi slave modules both of which use four wire interfaces: mosi, miso, clk and ss # . their main purpose is to send data from main memory to the attached spi master, and / or receive data and send it to main memory. the spi slave is c ontrolled by the internal cpu using internal memory mapped i/o registers. it operates from the main system clock, although sampling of input data and transmission of output data is controlled by the spi clock (clk ). an spi transfer can only be initiated by the spi master and begins with the slave select signal being asserted. this is followed by a data byte being clocked ou t with the master supplying clk . the master always supplies the first byte, which is called a command byte. after this the desired numbe r of data bytes are transferred before the transaction is terminated by the master de - asserting slave select. an spi master is able to abort a transfer a t any time by de - asserting its ss # output. this will cause the slave to end its current transfer and re turn to idle state. e x t e r n a l - s p i m a s t e r v n c 2 - s p i s l a v e c l k s s # m i s o m o s i 42 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 6.3.1 spi slave signal descriptions 64 pin package available pins 48 pin package available pins 32 pin package available pins name type description 11, 15, 19, 24, 28, 39, 43, 47, 51, 57, 61 11, 15, 20, 31, 35, 41, 45 11, 23 29 spi_s0_clk spi_s1_clk input slave clock input 12, 16, 20, 25, 29, 40, 44, 48, 52, 58, 62 12,16, 21, 32, 36, 42, 46 12, 24, 30 spi_s0_mosi spi_s1_mosi input mater out slave in synchronous data from master to slave 13, 17, 22, 26, 31, 41, 45, 49, 55, 59, 63 13, 18, 22, 33, 37, 43, 47 14, 25, 31 spi_s0_miso spi_s1_miso output master in slave out synchronous data from slave to master 14, 18, 23, 27, 32, 42, 46, 50, 56, 60, 64 14, 19, 23, 34, 38, 44, 48 15, 26, 32 spi_s0 _ss# spi_s1 _ss# input slave chip select table 6 . 5 data and control bus signal mode options - spi slave interface 43 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 6.3.2 full duplex in full duplex mode, the spi slave send s data on miso line at the same time as it receives data on mosi . during the comm and phase this data is always the slave status byte. for a write command, write data can be streamed out of mosi and status can be sent during each write phase from slave to master. as long as the slave status indicates that it can receive more data, the m aster can continue to stream further write bytes. figure 6 . 5 is an example of this. figure 6 . 5 full duplex data master write when the master is performing a data read, the data and status both need to share the same pin (miso). in this case the master and slave will exchange command and status bytes, followe d by the slave sending its data. if the master keeps ss # active the slave will se nd a further status byte after the data followed by another data byte. this continues until the master indicates the end of the communications by raising ss #. figure 6 . 6 is an example of this. figure 6 . 6 full duplex data master read s s # m i s o m o s i 8 b i t c m d w 0 w 1 w 2 s t a t u s s t a t u s s t a t u s s t a t u s s s # m i s o m o s i 8 b i t c m d s t a t u s r 0 s t a t u s r 1 44 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 the command and status formats for this mode can be seen in figure 6 . 7 below with a description of each field in table 6 . 6 : command: status: figure 6 . 7 spi command and status structure field description a2:a0 address of slave bein g used in a multi - slave environment. this would typically be used in the scenario where a shared data bus is used. r/w # set to 1 for a read and 0 for a write. z tri - stated. txe transmit empty. when 1 the slave transmit buffer has no new data to tr ansmit. when 0 the slave transmit buffer does have new data. rxf receive full. when 1 the slave receive buffer has new data which has not been read yet. when 0 the slave receive buffer is empty and can be safely written to. ac k set to 1 when a s lave has correctly decoded its address. table 6 . 6 spi command and status fields a2 a1 a0 r/w # z z z z z z z z txe rxf ack z 45 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 6.3.3 half duplex, 4 pin in half duplex mode, the mosi signal is shared for both master to slave and slave to master communications. when using 4 pins, the miso signal carries the status bits. the master initiates data write transfer, this by asserting ss # and then sending out a command byte. this has the same format as that shown in figure 6 . 7 . the slave send s status during this command phase and if this indicates that the slave can accept data the master will follow this up with a byte of write data. if the status continues to indicate that more data can be written, a whole stream of data can b e written following one single command. the operation completes when the master raises ss # again . figure 6 . 8 is an example of this. figure 6 . 8 half duplex data master write data reads are similar, apart from the mosi pin changing from slave input to slave output after the command phase. figure 6 . 9 is an example. in this diagram, the master drives the command while the slave returns with status. then the mosi buffers are turned round and a stream of read data is sent from the slave to the master on the mosi signal. figure 6 . 9 half duplex data master read s s # m i s o m o s i 8 b i t c m d w 0 w 1 w 2 s t a t u s s t a t u s s t a t u s s t a t u s s s # m i s o m o s i 8 b i t c m d r 0 r 1 r 2 s t a t u s s t a t u s s t a t u s s t a t u s m a s t e r t o s l a v e s l a v e t o m a s t e r 46 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 6.3.4 half duplex, 3 pin the 3 pin half duplex mode eliminates the miso pin from the protocol. this means that status bytes need to be sent on the mosi pin. again the master init iate s a transfer by asserting ss # and sending out a command byte. the slave send s status back to the master. if a write has been requested and the status indicates that the slave can accept data, mosi should be changed to an out put again and data will be sent from master to slave. following this data, t he slave will se nd a further status byte if ss # remains active. if the status indicates that more data can be written, the next data byte can be sent to the slave and t his process continues until ss # is de - asserted. figure 6 . 10 is an example of this: figure 6 . 10 half duplex 3 - pin data master write data reads are similar expect that after the command byte all data transfer is from slave t o master. figure 6 . 11 is an example of this: figure 6 . 11 half duplex 3 - pin data master read s s # m o s i 8 b i t c m d m a s t e r t o s l a v e s t a t u s w 0 s t a t u s w 1 s l a v e t o m a s t e r s l a v e t o m a s t e r m a s t e r t o s l a v e m a s t e r t o s l a v e s s # m o s i 8 b i t c m d m a s t e r t o s l a v e s t a t u s r 0 s t a t u s r 1 s l a v e t o m a s t e r 47 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 6.3.5 unmanaged mode the vnc2 spi slave also suppo rt s an unmanaged spi mode. this is a simple data exchange be tween master and slave. it operate s in the standard 4 pin mode ( ss #, c l k, mosi and miso) with all transfers controlled by the spi master. when the cpu wants to send da ta out of the spi slave it w rite s this into the spi_slave_data_tx register. this will then be moved into the transfer shift register to wait for the spi master to request it. the spi maste r will at some point assert ss # and start clocking data on mosi with sck. as this is shifted int o the transfer shift register, the spi slave will also be shifting data in the opposite direction on miso. at the end of the transfer the spi slave copies the received data from the shift register to spi_slave_data_rx as seen in figure 6 . 12 . figure 6 . 12 unmanaged mode transfer diagram s p i c l k d i v 0 1 2 3 4 5 6 7 r x s h i f t r e g i s t e r s p i m a s t e r s p i s l a v e s s # c l k m o s i m i s o 0 1 2 3 4 5 6 7 s h i f t r e g i s t e r 0 1 2 3 4 5 6 7 s h i f t r e g i s t e r 0 1 2 3 4 5 6 7 t x s h i f t r e g i s t e r 48 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 6.3.6 vnc1l legacy interface vnc2 spi is compatible with the spi slave of vnc1l . this is a custom protocol u si ng 4 wires and will be explained here. the master asserts the slave select, but in this case it is an active high signal. following this, a 3 bit command is sent on the mosi pin (see figure 6 . 15 for command structu re). this has instructions on whether a read or write is requested and if data or status is to be sent. for a data write, 8 bits of data are sent on mosi followed by a status bit being returned on miso. if this bit is 0 it means the data write was succes sful. if it is 1 it means that internal buffer was full and the write should be repeated. finally, the slave select is de - asserted. see figure 6 . 13 for an example of this . figure 6 . 13 vnc1l mode data write data reads are similar, with the data from slave to master coming on the miso pin. if the status bit is 0 it means the data byte sent is new data that has not been read before. if it is 1 it means that it i s old data. see figure 6 . 14 for an example. figure 6 . 14 vnc1l mode data read 49 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 the command and status formats for this mode can be seen in figure 6 . 15 below with a descrip tion of each field in table 6 . 7 . command: data: status: figure 6 . 15 vnc1l compatible spi command and status structure field description start driven to 1. r/w if set to 1, the spi master wishes to read from the slave. if set to 0, the spi master wishes to write to the slave. addr if set to 1, a read operation will return the status byte in the data phase. a write will have no effect. if set to 0, a read or a write will operate on the data register. d7:d0 data. status when 0 this means a read or write was successful. when 1 it means a re ad contains old data, or a write did not work and needs retried. table 6 . 7 spi command and status fields 6.3.6.1 spi setup bit encoding the vnc1l compatible spi interface differs from most other impl ementations in th at it uses a 12 clock sequence to transfer a single byte of data. in addition to a start state, the spi master must send two setup bits which indicate data direction and target address. the encoding of the setup bits is shown in table 6 . 8 . a single data byte is transmitted in each spi transaction, with the most significant bit transmitted first. after each transaction vnc2 return s a single s tatus b it. this indicates if a data write was successful or a data read wa s valid. direction (r/w) target address operation meaning 1 0 data read retrieve byte from transmit buffer 1 1 status read read spi interface status 0 0 data write add byte to receive buffer 0 1 n/a n/a table 6 . 8 spi setup bit encoding start r/w addr d7 d6 d5 d4 d3 d2 d1 d0 status 50 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 the vnc2 spi i nterface uses 4 signal lines : sclk, ss , mosi and miso . the signals mosi , miso and ss are always clocked on the rising edge of the sclk signal. ss signal must be raised high for the duration of the entire tra nsaction. for data transactions, the ss must be released for at least one clock cycle after a transaction has completed. it is not necessary to release ss between status read operations. the start state of mosi and ss high on the rising edge of sclk ini tiates the transfer. the transfer finishes after 13 clock cycles, and the next transfer starts when mosi is high during the rising edge of clk. the following figure 6 . 16 and table 6 . 9 give details of the bus timing requirements. figure 6 . 16 spi slave mode timing table 6 . 9 s pi slave data timing 6.3.6.2 spi master data read transaction in vnc1l legacy mode the spi master must periodically poll for new data in vnc2 transmit buffer. it is recommended that this is done first before sending any command. the start and setup sequence is se nt to vnc2 by the spi master , see figure 6 . 17 . the vnc2 clocks out data from its transmit buffer on subsequent rising edge clock cycles provided by the spi master . this is followed by a status bit generated by vnc2 . the data read status bit is defined in table 6 . 10 . if the status bit indicates new data then the byte received is valid. if it indicates old data then the transmit buffer i n vnc2 is empty and the byte of data re ceived in the current transaction should be disregarded. time description minimum typical maximum unit t1 sc lk period 79.37 83.33 ns t2 sc lk high period 39.68 41.67 3 9.68 ns t3 sc lk low period 39.68 41.67 39.68 ns t4 sc lk driving edge to miso/mosi 0.5 14 ns t5 miso/ss setup time to sample sc lk edge 3 ns t6 miso/ss hold time from sample sc lk edge 3 ns 51 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 status bit meaning 0 new data data in current transaction is valid data. byte removed from transmit buffer. 1 old data this same data has been read in a previous read cycle. repeat the read cyc le until new data is received. table 6 . 10 spi master data read status bit figure 6 . 17 spi master data read (vnc2 slave mode ) the status bit is only valid un til the next rising edge of sclk after the last data bit. during the data read operation the ss signal must not be de - asserted. the transfer completes after 12 clock cycles and the next transfer can begin when mosi and ss are high during the rising edge of sclk. 6.3.6.3 spi master data write transaction in vnc1l legacy mode during an spi master data write operation the start and setup sequence is sent by the spi master to vnc2 , see figure 6 . 18 . t his is followed by the spi m aster transmitting each bit of the data to be written to vnc2. the vnc2 then responds with a status bit on miso on the rising edge of the next clock cycle. the spi master must read the status bit at the end of each write transaction to determine if the dat a was written successfully to vnc2 receive buffer. the data write status bit is defined in table 6 . 11 . t he status bit is only valid until the next rising edge of sclk after the last data bit. if the status bit indic ates accept then the byte transmitted has been added to vnc2 receive buffer. if it shows reject then the receive buffer is full and the byte of data transmitted in the current transaction should be re - transmitted by the spi master to vnc2. any application should poll vnc2 receive buffer by retrying the data write operation until the data is accepted. status bit meaning 0 accept data from the current transaction was accepted and added to the receive buffer 1 reject write data was not accepted. retry the same write cycle. table 6 . 11 spi master data write status bit 52 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 figure 6 . 18 spi slave mode data write 6.3.6.4 spi master status read transaction in vnc1l legacy mode t he vnc2 has a status byte which determines the state of the receive and transmit buffers. the spi master must poll vnc2 and read the status byte . the start and setup sequence is sent to vnc2 by the spi master, see figure 6 . 19 . the vnc2 clocks out its status byte on subsequent rising edge clock cycles from the spi master . this is followed by a status bit generated by vnc2 (also on the miso ) which will always be zero (indicating new data). the meaning of the bits wi thin the status byte sent by vnc2 during a status read operation is described in table 6 . 12 . the result of the status read transaction is only valid during the transaction itself. data read and data write transacti ons must still check the status bit during a data read or data write cycle regardless of the result of a status read operation. bit description description 0 rxf# receive buffer full 1 txe# transmit buffer empty 2 - not used 3 - not used 4 rxf irqen receive buffer full interrupt enable 5 txe irqen transmit buffer empty interrupt enable 6 - not used 7 - not used table 6 . 12 spi stat us read byte C bit descriptions figure 6 . 19 spi slave mode status read 53 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 6.4 serial peripheral interface C spi master figure 6 . 20 spi master block diagram the spi master interface is used to interface to applications such a s sd cards. the spi master provide s the following features: ? synchronous serial data link. ? full an d half duplex data transmission. ? serial clock with programmabl e frequency, polarity and phase. ? one slave select output. ? programmable delay b etween negative edge of slave select and start of transfer. ? sd card interface . ? an interface thats compatible with the vlsi vs1033 sci mode used for vmusic capability the spi master only clocks in and out data that the vnc2 cpu sets up in its register spac e. the vnc2 cpu interprets the data words that are to be sent and received. 6.4.1 spi master signal descriptions. table 6 . 13 shows the spi master signals and the available pins that they can be mapped to depending on t he package size. further details on the configuration of input and output signals are available in s ection 5 - i/o multiplexer . 64 pin package available pins 48 pin package available pins 32 pin package available pins name type description 11, 15, 19, 24, 28, 39, 43, 47, 51, 57, 61 11, 15, 20, 31, 35, 41, 45 11, 23 29 spi_m_clk output spi master c lock input v n c 2 - s p i m a s t e r e x t e r n a l - s p i s l a v e c l k s s # m i s o m o s i 54 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 64 pin package available pins 48 pin package available pins 32 pin package available pins name type description 12, 16, 20, 25, 29, 40, 44, 48, 52, 58, 62 12,16, 21, 32, 36, 42, 46 12, 24, 30 spi_m_mosi output mas ter out slave i n synchronous data from master to slave 13, 17, 22, 26, 31, 41, 45, 49, 55, 59, 63 13, 18, 22, 33, 37, 43, 47 14, 25, 31 spi_m_miso input master in slave o ut synchronous data from slave to master 14, 18, 23, 27, 32, 42, 46, 50, 56, 60, 64 14, 19, 23, 34, 38, 44, 48 15, 26, 32 spi_m_ ss _0# output active low slave select 0 from master to slave 0 11, 15, 19, 24, 28, 39, 43, 47, 51, 57, 61 11, 15, 20, 31, 35, 41, 45 11, 23 29 spi_m_ ss _1# output active low slave select 1 from master to slave 1 table 6 . 13 spi master signal names the main purpose of the spi master block is to transfer data between an external spi interface and the vnc2 . it does this under the control of the cpu and dma eng ine via the on chip i/o bus. an spi master interface transfer can only be initiated by the spi master and begins with the slave select signal being asserted. this is followed by a data byte being clocked out with the master supplying sclk. the master alway s supplies the first byte, which is called a command byte. after this the desired number of data bytes are transferred before the transaction is terminated by the master de - asserting slave select. the spi master will transmit on mosi as well as receive on miso during every data stage. at the end of each byte spi_tx_done and spi_rx_full_int are set. figure 6 . 21 typical spi master t iming and table 6 . 14 spi master timing show an example of this. 55 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 figure 6 . 21 typical spi master t iming table 6 . 14 spi master timing time description minimum typical maximum unit t 1 sc lk period 39.68 41.67 ns t 2 sc lk high period 19.84 20.84 21.93 ns t 3 sc lk low period 19.84 20.84 21.93 ns t 4 sc lk driving edge to mosi/ss - 1.5 3 ns t 5 miso setup time to sample sc lk edge 6.5 ns t 6 miso hold time from sample sc lk edge 0 ns 56 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 6.5 debugger interf ace the purpose of the debugger interface is to provide the integrated development environment ( ide ) with the following capabilities: ? flash erase, write and program. ? application debug - application code can have breakpoints, be single stepped and can be h alted. ? detailed inter nal debug - memory read/write access. the single wire interface has the following features: ? half duplex operation ? 1mbps speed ? 1 start bit ? 1 stop bit ? 8 data bits ? pull up further information of the debugger interface is available in an application note an_138 vinculum - ii debug interface description . 6.5.1 debugger interface signal description 64 pin package availab le pins 48 pin package available pins 32 pin package available pins name type description 11, 15, 19, 24, 28, 39, 43, 47, 51, 57, 61 11, 15, 20, 31, 35, 41, 45 11, 23 29 d ebug_if input/ output debugger interface table 6 . 15 debugger signal name 57 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 6.6 parallel fifo C asynchronous mode parallel fifo asynchronous mode known as 245 , is functionally the same as the o ne that is present in vnc1l has an eight bit data bus, individual read and write strobes and two hardware flow control signals. 6.6.1 fifo signal descriptions the parallel fifo interface signals are described in table 6 . 16 t hey can be programmed to a choice of i/o pins depending on the package size. further det ails on the configuration of input and output signals are available in s ection 5 - i/o multiplexer . 64 pin package available pins 48 pin package available pins 32 pin package available pins name type description 11, 15, 19, 24, 28, 39, 43, 47, 51, 57, 61 11, 15, 20, 31, 35, 41, 45 11, 23 29 fifo_data[0] i/o fifo data bus bit 0 12, 16, 20, 25, 29, 40, 44, 48, 52, 58, 62 12,16, 21, 32, 36, 42, 46 12, 24, 30 fifo_data[1] i/o fifo data bus bit 1 13, 17, 22, 26, 31, 41, 45, 49, 55, 59, 63 13, 18, 22, 33, 37, 43, 47 14, 25, 31 fifo_data[2] i/o fifo data bus bit 2 14, 18, 23, 27, 32, 42, 46, 50, 56, 60, 64 14, 19, 23, 34, 38, 44, 48 15, 26, 32 fifo_data[3] i/o fifo data bus bit 3 58 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 64 pin package available pins 48 pin package available pins 32 pin package available pins name type description 11, 15, 19, 24, 28, 39, 43, 47, 51, 57, 61 11, 15, 20, 31, 35, 41, 45 11, 23 29 fifo_data[4] i/o fifo data bus bit 4 12, 16, 20, 25, 29, 40, 44, 48, 52, 58, 62 12,16, 21, 32, 36, 42, 46 12, 24, 30 fifo_data[5] i/o fifo data bus bit 5 13, 17, 22, 26, 31, 41, 45, 49, 55, 59, 63 13, 18, 22, 33, 37, 43, 47 14, 25, 31 fifo_data[6] i/o fifo data bus bit 6 14, 18, 23, 27, 32, 42, 46, 50, 56, 60, 64 14, 19, 23, 34, 38, 44, 48 15, 26, 32 fifo_data[7] i/o fifo data bus bit 7 11, 15, 19, 24, 28, 39, 43, 47, 51, 57, 61 11, 15, 20, 31, 35, 41, 45 11 , 23 29 fifo_rxf # output when high, do not read data from the fifo. when low, there is data available in the fifo which can be read by strobing fifo_rd # low, then high. 59 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 64 pin package available pins 48 pin package available pins 32 pin package available pins name type description 12, 16, 20, 25, 29, 40, 44, 48, 52, 58, 62 12,16, 21, 32, 36, 42, 46 12, 24, 30 fifo _txe # output when high, do not write data into the fifo. when low, data can be written into the fifo by strobing fifo_wr# high, then low. 13, 17, 22, 26, 31, 41, 45, 49, 55, 59, 63 13, 18, 22, 33, 37, 43, 47 14, 25, 31 fifo_rd # input enables the current fifo data byte on d0...d7 when low. fetches the next fifo data byte (if available) from the receive fifo buffer when fifo_rd # goes from high to low 14, 18, 23, 27, 32, 42, 46, 50, 56, 60, 64 14, 19, 23, 34, 38, 44, 48 15, 26, 32 fifo_wr # input writes the data byte on the d0...d7 pins into the transmit fifo buffer when fifo_wr# goes from high to low. table 6 . 16 data and contro l bus signal mode options - parallel fifo interface 6.6.2 read / write transaction asyn chronous fifo mode when in asynchronous fifo interface mode, the timing o f read and write operation s on the fifo interface are shown in figure 6 . 22 and table 6 . 17 . in async hronous mode an external device can control data transfer driving fifo_ wr# and fifo_ rd# inputs. in contrast to synchronous mode, in asynchronous mode the 245 fifo module generates the output enable en# signal. en# signal is effectively the read signal rd#. current byte is available to be read when fifo_ rd# goes low. when fifo_ rd# goes high, fifo_ rxf# output will also go high. it will only become low again when there is another byte to read. when fifo_ wr# goes low fifo_ txe# flag will always go high. fifo _ txe# goes low again only when there is still space for data to be written in to the module. 60 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 figure 6 . 22 asynchronous fifo mode read / write cycle time description minimum maximum unit t1 rd# inactive to rxf# 1 14 ns t2 rxf# inactive after rd# cycle 100 ns t3 rd# to data 1 14 ns t4 rd# active pulse width 30 ns t5 rd# active after rxf# 0 ns t6 wr# active to txe# inactive 1 14 ns t7 txe# inactive after wr# cycle 100 ns t8 data to txe# active setu p time 5 ns t9 data hold time after wr# inactive 5 ns t10 wr# active pulse width 30 ns t11 wr# active after txe# 0 ns table 6 . 17 asynchronous fifo mode read / write timing 61 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 6.7 parallel fifo C s ynchronous m ode the parallel fifo synchronous mode has an eight bit data bus, indivi dual read and write strobes, two hardware flow control signals , an output enable and a clock out . the synchronous fifo mode uses the parallel fifo interface signals detailed in table 6 . 16 and an additional two signals detailed in table 6 . 18 . this mode is not available on the 32 pin packages. 64 pin package available pins 48 pin package available pins 32 pin package available pins name type description 11, 15, 19, 24, 28, 39, 43, 47, 51, 57, 61 11, 15, 20, 31, 35, 41, 45 11, 23 29 fifo_oe# i/o fifo output enable 12, 16, 20, 25, 29, 40, 44, 48, 52, 58, 62 12,16, 21, 32, 36, 42, 46 12, 24, 30 fifo_clkout i/o fifo c lock out table 6 . 18 synchronous fifo control signals 62 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 6.7.1 read / write transaction s ynchronous fifo mode when in synchronous fifo interface mode, the timing of read and write operations on the fifo i nterface are shown in figure 6 . 23 synchronous fifo mode read / write cycle and table 6 . 19 synchronous fifo mode read / write timing in synchronous mode data can be transmit ted to and from the fifo module on each clock edge. an external device synchronises to the clkout output and it also has access to the output enable oe# input to control data flow. an external device should drive output enable oe# low before pulling rd# li ne down. when bursts of data are to be read from the module rd# should be kept low. rxf# remains low when there is still data to be read. similarly when bursts of data are to be written to the module wr# should be kept low. txe# remains low when there is s till space available for the data to be written. figure 6 . 23 synchronous fifo mode read / write cycle 63 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 time description minimum typical maximum unit t1 c lkout period 20.83 ns t2 c lkout high peri od 9.38 10.42 11.46 ns t3 c lkout low period 9.38 10.42 11.46 ns t4 c lkout to rxf# 1 7.83 ns t5 c lkout to read data valid 1 7.83 ns t6 oe# to read data valid 1 7.83 ns t7 c lkout to oe# 1 7.83 ns t8 rd# setup time 12 ns t9 rd# hold time 0 ns t10 c lkout to txe# 1 7.83 ns t11 write data setup time 12 ns t12 write data hold time 0 ns t13 wr# setup time 12 ns t14 wr# hold time 0 ns table 6 . 19 synchronous fifo mode read / write timing 6.8 g eneral purpose timers in vnc2 there are 4 general purpose timers available. three are available to the designer and one is reserved for the rtos. the timers have the following features: ? 16 bit ? count down ? one shot and auto - reload ? enable ? interrupt on zero 6.9 pulse width modulation vnc2 provides 8 pulse width modulation (pwm) outputs. these can be used to generate pwm signals which can be used to control motors, dc/dc converters, ac/dc supplies, etc. further information is available in an application n ote an_14 0 - vinculum - ii pwm example . the features of the pwm module are as follows: ? 8 pwm outputs ? a trigger input ? 8 - bit prescaler ? 16 - bit counter 64 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 ? generation of up to 4 - pulse signal with controlled output enable and configurable initial state ? interrupt a single pwm cycle can have up to 4 pulses (8 edges) . the pwm block uses a 16 - bit counter to determine the period of a single pwm cycle. this counter counts sy stem clocks which can also be divided by an optional 8 - bit prescaler. the pwm driver s allow the user to select when pwm output toggles. these values correspond to the values of 16 - bit counter. for example, on the timing diagram below - figure 6 . 24 , the 16 - bit counter counts to 23 and pwm_out[0] output toggles when the counters current value is equal to 7, 8, 12, 14, 15, 16, 19 and 22. figure 6 . 24 pwm C timing di agram the user can also select the initial state of each of the pwm outputs (hi or low). pwm outputs can also be enabled continuously or a cycle can be repeated 1..255 times. the pwm cycle can be started by the pwm driver or externally using a trigger inp ut. 6.10 general purpose input output vnc2 provides up to 4 0 configur able input/output pins depending on the package . the input/output pins are connected to ports a through e. these ports are controlled by the vnc2 cpu . all ports are configurable to be ei ther inputs or outputs and allow level or edge driven interrupts to be generated . to simplify the use of the 40 available gpio signals, they have been grouped into 5 "ports", identified as a, b, c, d and e. each port is 1 byte wide and the rtos drivers will a llow each port to be individually accessed . each gpio signal is mapped on to a bit of the por t value. for example, gpi o [ a 0] is the least significant bit of the value read from or written to gpio port a. similarly, gpio [ a 7] is the most significant bit of the value read from or written to gpio port a (see figure 6 . 25 gpio port groups ) each pin can be individually configured as input or output. gpio port a supports an interrupt that can be used to detect a state c hange of any of its 8 pins. port b features a more sophisticated set of 4 configurable interrupts that can be associated with individual pins and supports several conditions such as positive edge, negative edge, high or low. figure 6 . 25 gpio port groups p o r t a g p i o [ a 0 ] g p i o [ a 1 ] g p i o [ a 2 ] g p i o [ a 3 ] g p i o [ a 4 ] g p i o [ a 5 ] g p i o [ a 7 ] g p i o [ a 6 ] p o r t b g p i o [ b 0 ] g p i o [ b 1 ] g p i o [ b 2 ] g p i o [ b 3 ] g p i o [ b 4 ] g p i o [ b 5 ] g p i o [ b 7 ] g p i o [ b 6 ] p o r t c g p i o [ c 0 ] g p i o [ c 1 ] g p i o [ c 2 ] g p i o [ c 3 ] g p i o [ c 4 ] g p i o [ c 5 ] g p i o [ c 7 ] g p i o [ c 6 ] p o r t d g p i o [ d 0 ] g p i o [ d 1 ] g p i o [ d 2 ] g p i o [ d 3 ] g p i o [ d 4 ] g p i o [ d 5 ] g p i o [ d 7 ] g p i o [ d 6 ] p o r t e g p i o [ e 0 ] g p i o [ e 1 ] g p i o [ e 2 ] g p i o [ e 3 ] g p i o [ e 4 ] g p i o [ e 5 ] g p i o [ e 7 ] g p i o [ e 6 ] 65 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 7 usb interfaces vnc2 has two usb 1.1 and usb 2.0 compliant interf aces available either as a usb h ost or slave device capable of supporting 1.5mb/s (low speed) and 1 2mb/s (f ull spee d) transactions. the usb specification defines 4 transfer types that are all supported by vnc2: ? interrupt transfer: used for legacy devices where the device is periodically polled to see if the device has data to transfer e.g. mouse, keyboard. vnc2 interr upt transfers are valid for low - and full - speed transactions. ? bulk t ransfer: used for transferring large blocks of data that have no periodic or transfer rate r equirement e.g. usb to rs232 (ft232r device) , memory sticks . vnc2 bulk transfers are only valid for full - speed transactions. ? isochronous t ransfer: used for transferring data that re quires a constant delivery rate e.g. web cam, wireless modem. vnc2 isochronous transfers are only valid for full - speed transactions. ? control t ransfer: used to transfer s pecific requests to all types usb devices (most commonly us ed during device configuration). vnc2 control transfers are valid for low - and full - speed transfers. usb 2.0 - 480mb/s (high speed) transactions are not supported as the power requirements are dee med excessive for vnc2 target applications. vnc2 configured to full speed is supported. vnc2 has tw o main usb modes of operation: h ost mode or c lient (or slave) mode. as a c lient , vnc2 is able to connect to a pc and act as a usb peripheral . at the same tim e as being a client the second usb interface is also able to act as a h ost and connect to a second usb device using two separate ports ( i.e. port 0 C host port 1 - client ) . each usb interface can be either a host or a client . it is not possible to change from host to client or client to host on - the - fly . the following diagram s in figure 7.1 give examples of possible modes of operation: figure 7 . 1 usb modes v n c 2 p o r t 1 p o r t 0 b o m s f l a s h d i s k u s b d e v i c e p o r t 0 a n d 1 i n h o s t m o d e v n c 2 p o r t 1 p o r t 0 p o r t 0 i n s l a v e m o d e u s b h o s t v n c 2 p o r t 1 p o r t 0 p o r t 0 i n s l a v e m o d e a n d p o r t 1 i n h o s t m o d e u s b h o s t b o m s f l a s h d i s k v n c 2 p o r t 1 p o r t 0 p o r t 0 a n d 1 i n s l a v e m o d e ( n u l l m o d e m t y p e a p p l i c a t i o n ) u s b h o s t u s b h o s t 66 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 8 firmware vnc2 firmw are model has evolved considerably since vinc1l . for reasons of code maintainability, performance, stability and ease of use from the point of view of the customer, vnc2 has a modular firmware model. vnc2 firmware can be separated into 4 categories: ? vnc 2 real - time operating system (rtos) . ? vnc2 device drivers . ? user applications C tool c hain . ? precompiled firmware. 8.1 rtos the vnc2 rtos (vos) is a pre - emptive priority - based multi - tasking operating system. vos has been developed by ftdi and is available to cu stomers for use in their own vnc2 based systems free of charge. vos is supplied as linkable object files. a full explanation and how to use vos is available in a separate application note which can be downloaded from the ftdi website . 8.2 device drivers to facilitate communication between user applications and the vnc2 hardware peripherals ftdi provides device drivers which operate with vos. in addition to the ha rdware device drivers, ftdi provide s function drivers (a vailable from the ftdi website ) which build upon the basic hardware device driver functionality for a specific purpose. for example, drivers for standard usb device classes may be created which build upon the usb h ost hardware driver to implement a boms class, cdc, printer class or even a specific vendor class device driver. 8.3 firmware C software devel op ment tool c hain the vnc2 provides customers with the opportunity to customise the firmware and perform useful task s without an external mcu. a firmware application note is available to download from the ftdi website , this give further details and operating instructions. the vnc2 software development t oolchain consists of the fo llowing components : ? compiler the compiler will take high - level source code and compile it into object code or direct to programmable code. ? linker the linker will take object code and libraries and link the code to produce either libraries or programmable code. it is designed to be as hardware independent as possible to allow reuse in future hardware devices. ? debugge r the debugger allows a programmer to test code on the hardware platform using a special comm unication channel to the cpu. it is also used to d ebug code C run, stop, single step, breakpoints etc. ? ide all compiler, simulator and debugger functions are integrated into a single application for programmers. it provides a specialised text editor which is used generally used to develop application code , debugging and simulation. 67 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 8.4 precompil ed firmware vnc2 can be programmed with various pre - compiled f irmware profiles to allow a designer to easily change the functionality of the chip. the following pre - compiled rom files are currently available: ? v2 dap f irmware: usb host for single flash disk and general p urpose usb peripherals. selectable uart , fifo or spi interface command monitor . offers a migration path from vnc1l designs with vdap firmware. ? v2dps firmware: usb host for single flash disk and general purpose usb peripherals and usb peripheral emulating a ft232 on a host computer. offers a migration path for vnc1l designs with vdps. ? v2f2f firmware: usb host for two flash disks with file copy functions. offers a migration path for vnc1l designs with vf2f firmware. ? cdc modem sample application: demonstrates connection of a cdc device to usb port 1 by establishing a link between the cdc device and the uart of the vnc2. ? usbhost ft232 uart echo sample application: demonstrates emulation of a ftdi ft232 device on usb port 1. data is looped back. designers are advised to refer to the ftdi website for the most current details on available firmware. 68 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 9 device characteristics and ratings 9.1 absolut e maximum ratings the absolute maximum ratings for vnc2 are shown in table 9 . 1 . these are in accordance with the absolute maximum rating system (iec 60134). exceeding these may cause permanent damage to the device . parameter value unit storage temperature - 6 5 to + 150 c floor life (out of bag) at factory ambient ( 30c / 60% relative humidity) 168 (ipc /jedec j - std - 033a msl level 3 c ompliant)* hours ambient temperature (power applied) - 40 to + 85 c vcc sup ply voltage 0 to +3.6 3 v vc c _io 0 to +3.6 3 v vc c _pll_in 0 to + 1.98 v dc input voltage - usbdp and usbdm - 0.5 to +(vcc +0.5) v dc input voltage - xtin - 0.5 to +(( 1.8v vc c pll in ) +0.5) v dc input voltage - high impedance bidirectional - 0.5 to +5.00 v dc input voltage - all other inputs - 0.5 to +(vcc +0.5) v dc output c urrent - outputs default 4 ** ma dc output c urrent - low impedance bidirectional default 4 ** ma table 9 . 1 absolute maximum ratings * if devices are stored out of the packaging beyond this time limit the devices should be baked before use. the devices should be ramped up to a temperature of 125c and baked for up to 17 hours. ** the drive strength of the output stage may be configured f or either 4ma, 8ma, 12ma or 16ma depending on the register setting controlled within the firmware. the default is 4ma. 69 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 9.2 dc characteristics dc characteristics (ambient temperature - 40?c to +12 5 ?c) parameter description minimum typical maximum units conditions vcc1 vc c operating supply voltage 1.62 1.8 1.98 v vcc2 vc c io operating supply voltage 2.97 3.3 3.63 v vc c _pll vc c_pll operating supply voltage 1 .62 1.8 1.98 v icc1 operating supply c urrent 48mhz 25 ma normal operation icc2 operating supply c urrent 24mhz 16 ma low power mode icc3 operating supply c urrent 12mhz 8 ma lowest power mode icc4 operating supply c urrent 128 a usb suspend table 9 . 2 operating voltage and current parameter description minimum typical maximum units conditions voh output voltage high 2.4 v i source = 8ma vol output voltage low 0.4 v i sink = 8ma vin input s witching threshold 1.5 v table 9 . 3 i/o pin characteristics 70 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 parameter description minimum typical maximum units conditions uvoh i/o pins static output ( high) 2.8 v uvol i/o pins stat ic output ( low ) 0.3 v uvse single ended rx threshold 0.8 2.0 v uc om differential c ommon mode 0.8 2.5 v uvdif differential input sensitivity 0.2 v udrvz driver output impedance 3 6 9 ohms table 9 . 4 usb i/o pin (usbdp, usbdm) characteristics parameter description minimum typical maximum units conditions vc c k power supply of internal core cells and i/o to core interface 1.62 1.8 1.98 v 1.8v power supply vc c 18io power supply of 1.8v osc pad 1.62 1.8 1.98 v 1.8v power supply t j operating junction temperature - 40 25 125 c i in input leackage current - 10 1 10 a i in = vc c 18io or 0 v i oz tri - state output leakage current - 10 1 10 a table 9 . 5 crystal oscillator 1.8 volts dc characteristics 71 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 9.3 esd and latch - up specifications description specification human body mode (hbm) tbd machine mode (mm) tbd c harged device mode (c dm) tbd latch - up > 200ma table 9 . 6 esd and latch - up specifications 72 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 10 ap plication examples 10.1 example vnc2 schematic (mcu C uart interface) vnc2 can be configured to communicate with a microcontroller using a uart interface. an example of this is shown in figure 10 . 1 . figure 10 . 1 vnc2 schematic (mcu C uart interface) note s : this sample circuit is not intended to be a complete design . it shows the minimum connections for a basic vnc2 c ircuit . the value of the capacitors connected to the crystal will depend on the requirements of the crystal. the 5v0_sw power signal assumes proper switching and over - current detection conform to the usb - if specifications for a usb host port. the 120uf capacitor should be a low - esr type. the value of the ferrite bead s may need adjusted for emi compatibility . input and output capacitors for the 3.3v regulator should be chosen according to the datasheet of the selected part. t he vnc2 outputs connect to the mcu inputs and mcu outputs to vnc2 inputs (txd to rxd and rts# to cts# in each direction). note for vnc2 - 48l 1b only: with t he 48 - pin lqfp package, pin 7 is not connected (vregout). the regulator output has an internal connection to vccpllin to accomm odate a migration path from vnc1l design s . in this case, pin 3 ( vccpllin ) requires only one 100nf capacitor to ground. all other packages require the external circuitry shown to connect vregout to vccpllin. 73 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 11 package parameters vnc2 is available in six roh s compliant packages, three qfn packages (64qfn, 48qfn & 32qfn) and three lqfp packages (64lqfp, 48lqfp & 32lqfp). all package s are lead (pb) free and use a green compound. the package s are fully compliant with european union directive 2002/95/ec. the me chanical drawing s of all six packages are shown in sections 11.2 to 11.7 C all dimensions are in millimetres. the solder reflow profile for all packages can be viewed in section 11.8 . 11.1 vnc2 package markings an example of the markings on each package is shown in figure 11 . 1 . the ftdi part number is too long for the 32 qfn package s o in this case the last two digits are wrapped down onto the date code line as shown in figure 11 . 2 . figure 11 . 1 package markings figure 11 . 2 markings C 32 qfn the last letter of the ftdi part number is the silicon revision number. this may change from a to b to c, etc. , . please check the part number for the mos t recent revision. l i n e 4 - d a t e c o d e y y - y e a r y e a r w w - w o r k w e e k x x x x x x x x x x f t d l y y w w v n c 2 - 6 4 q 1 a l i n e 3 C f t d i p a r t n u m b e r i n c l u d i n g r e v i s i o n . i n t h i s c a s e i t s h o w s r e v a . p l e a s e c h e c k f o r m o s t r e c e n t r e v i s i o n . l i n e 2 C w a f e r l o t n u m b e r l i n e 1 C f t d i l o g o x x x x x x x x x x f t d l 1 a y y w w v n c 2 - 3 2 q 74 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 11.2 vnc2 , lqfp - 32 package dimensions figure 11 . 3 lqfp - 32 package dimensions f t d l x x x x x x x x y y w w v n c 2 - 3 2 l 1 a p i n # 1 p i n # 3 2 75 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 11.3 vnc2 , qfn - 32 package dimensions figure 11 . 4 qfn - 32 package dimensions 1 x x x x x x x x f t d l 1 a y y w w v n c 2 - 3 2 q 1 76 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 11.4 vnc2 , lqfp - 48 package dimensions figure 11 . 5 lqfp - 48 package dimensions p i n # 1 0 . 2 5 1 . 6 0 m a x 1 2 o + / - 1 o 1 . 4 + / - 0 . 0 5 0 . 2 m i n 0 . 6 + / - 0 . 1 5 1 . 0 0 . 0 5 m i n 0 . 1 5 m a x 0 . 2 4 + / - 0 . 0 7 0 . 2 2 + / - 0 . 0 5 0 . 0 9 m i n 0 . 2 m a x 0 . 0 9 m i n 0 . 1 6 m a x 7 9 7 9 p i n # 4 8 0 . 5 0 . 2 2 + / - 0 . 0 5 x x x x x x x x f t d l y y w w v n c 2 - 4 8 l 1 a 77 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 11.5 vnc2 , qfn - 48 package dimensions figure 11 .2 qfn - 48 package dimensions 4 8 1 x x x x x x x x x x f t d l y y w w v n c 2 - 4 8 q 1 a 1 4 8 78 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 11.6 vnc2 , lqfp - 64 package dimensions figure 11 . 6 64 pin lqfp package details 1 0 1 0 1 2 1 2 0 . 2 5 1 . 6 0 m a x 1 2 o + / - 1 o 1 . 4 + / - 0 . 0 5 0 . 2 m i n 0 . 6 + / - 0 . 1 5 1 . 0 0 . 0 5 m i n 0 . 1 5 m a x 0 . 5 f t d l x x x x x x x x v n c 2 - 6 4 l 1 a y y w w 0 . 2 2 + / - 0 . 0 5 0 . 2 + / - 0 . 0 3 0 . 0 9 m i n 0 . 2 m a x 0 . 0 9 m i n 0 . 1 6 m a x p i n # 1 p i n # 6 4 79 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 11.7 vnc2 , qfn - 64 package dimensions figure 11 . 7 64 pin qfn package details x x x x x x x x x x f t d l y y w w v n c 2 - 6 4 q 1 a 80 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 11.8 solder reflow profile figure 11 . 8 all packages reflow solder pro file 81 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 profile feature pb free solder process (green material) snpb eutectic and pb free (non green material) solder process average ramp up rate (t s to t p ) 3c / second max. 3c / second max. preheat : - temperature min (t s min.) - temperature max ( t s max.) - time (t s min to t s max) 150c 200c 60 to 120 seconds 1 00c 150c 60 to 120 seconds time maintained above c ritical temperature t l : - temperature (t l ) - time (t l ) 217c 60 to 150 seconds 183c 60 to 150 seconds peak temperature (t p ) 260c see table 11 . 2 time within 5c of actual peak temperature (t p ) 30 to 40 seconds 20 to 40 seconds ramp down rate 6c / second max. 6c / second max. time for t= 25c to peak temperature, t p 8 minu tes max. 6 minutes max. table 11 . 1 reflow profile parameter values snpb eutectic and pb free (non green material) package thickness volume mm3 < 350 volume mm3 >=350 < 2.5 mm 235 +5/ - 0 c 220 +5/ - 0 c 2.5 mm 220 +5/ - 0 c 220 +5/ - 0 c pb free (green material) = 260 +5/ - 0 c table 11 . 2 package reflow peak temperature 82 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 12 contact information head office C glasgow, uk future technology devices internati onal limited unit 1, 2 seaward place, centurion business park glasgow g 41 1hh united kingdom tel: +44 (0) 141 429 2777 fax: +44 (0) 141 429 2758 e - mail (sales) sales 1 @ftdichip.com e - mail (support) support 1 @ftdichip.com e - mail (general enquiries) admin1@ftdichip.com branch office C taipei, taiwan future technology devices international limited (taiwan) 2f, no. 516, sec. 1, neihu road taipei 114 taiwan , r.o.c. tel: +886 (0) 2 879 7 1330 fax: +886 (0) 2 87 5 1 9737 e - mail (sales) tw.sales1@ftdichip.com e - mail (support) tw.support1@ftd ichip.com e - mail (general enquiries) tw.admin1@ftdichip.com branch office C tigard , oregon, usa future technology devices international limited (usa) 7130 sw fir loop tigard, or 97223 - 8160 usa tel: +1 (503 ) 547 0988 fax: +1 (503) 547 0987 e - mail (sales) us.sales@ftdichip.com e - mail (support) us.support@ftdichip.com e - mail (general enquiries) us.admin@ftdichip.com branch office C shanghai , china future technology devices international limited (china) room 1103, no. 666 west huaihai road, shanghai, 200052 c hina tel: +86 21 62351596 fax: +86 21 62351595 e - mail (sales) cn.sales@ftdichip.com e - mail (support) cn.support@ftdichip.com e - mail (general enquiries) cn.admin@ftdichip.com we b site http://ftdichip.com distributor and sales representatives please visit the sales network page of the ftdi web site for the contact details of our distributor (s) and sales representative(s) in your country. n either the whole nor any part of the information c ontained in, or the product desc ribed in this manual, may be adapted or re produced in any material or electronic form without the prior written cons ent of the copyright holder. this product and its documentation are s upplied on an as - is basis and no warranty as to their s uitability for any partic ular purpose is either made or implied. future t ec hnology d evices international l td will not accept any claim for damages hows oever aris ing as a res ult of us e or failure of this produc t. y our s tatutory rights are not affec ted. t his produc t or any variant of it is not intended for use in any medical appliance, device or sys tem in whic h the failure of the produc t might reasonably be expec ted to res ult in personal injury. t his doc ument provides preliminary information that may be s ubjec t to c hange without notice. n o freedom to us e patents or other intellec tual property rights is implied by the public ation of this documen t. future tec hnology devic es i nternational ltd, u nit 1 , 2 seaward p lace, c enturion business park, g las gow g 4 1 1 hh, u nited kingdom. sc otland registered c ompany n umber: sc136640 83 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 appendix a C references application , technical notes , toolchain download and p recompiled romfile links the following vnc2 documents and the full vinculum - ii toolchain software suite can be downloaded by clicking on the appropriate links below: technical note tn_108 vinculum chipset feature comparison technical note tn_118 vinculum - ii errata techni cal note application note a n_1 1 8 migrating vinculum designs from vnc1l to vnc2 - 48l1a application note a n_1 37 vinculum - ii io cell description application note a n_1 3 8 vinculum - ii debug interface description application note a n_1 39 vinculum - ii io mux explained application note a n_1 40 vinculum - ii pwm example application note a n_1 42 vinculum - ii tool c hain getting started guide application note a n_1 44 v inculum - ii io_mux configuration utility us er guide application note a n_1 45 vinculum - ii toolchain installation guide application note a n_1 51 vinculum - ii user guide vnc2 ftdi web page vinculum - ii web page the following application notes provide pre - compiled example rom files and complete source code to allow users to get started: ? application note an_182 : vnc2 uart to ft232 hostbridge ? application note an_183 : vnc2 uart to cdc modem bridge ? application note an_185 : vnc2 uart to usb hid class hostbridge ? application note an_186 : an spi slave to usb memory bridge ? application note an_187 : vnc2 uart to usb memory bridge ? app lication note an_192 : an spi master to a usb hid class host bridge ? application note an_193 : an spi master to a usb hid class host bridge ? application note an_194 : vnc2 uart to hid class device bridge ? application note an_195 : an spi master to uart bridge ? application note an_199 : vnc2 spi slave to hid class device bridge application note an_203 : loading vnc2 rom files using v2prog utility for the most up to date pre - compiled rom files, please refer to the following ftdi webpage http: //www.ftdichip.com/firmware/precompiled.htm 84 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 acronyms and abbreviations terms description usb universal serial bus fifo first in first out spi serial peripheral interface pwm pulse width modulation gpio general purpose input output i/o input / output vnc 1l vinculum - i vnc 2 vinculum - ii dma direct memory access ide integrated development environment boms bulk only mass storage uart universal asynchronous receiver/transmitter sie serial interface engine c pu c entral processing unit soc system - on - a - chip fat file allocation table rtos real time operating system vos vinculum operating system osi open system interconnection mosi master out slave in miso master in slave out se0 single ended zero emc u embedded micro central processing unit fpga field programmable gate array 85 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 appendix b C list of figures and tables list of tables table 1.1 part numbers ................................ ................................ ................................ .......................... 2 table 3.1 usb interf ace group ................................ ................................ ................................ ............. 16 table 3.2 power and ground ................................ ................................ ................................ ................. 16 table 3.3 miscellaneous signal group ................................ ................................ ................................ ... 17 table 3.4 default i/o configuration ................................ ................................ ................................ ...... 20 table 4.1 - peripheral pin requirements ................................ ................................ ............................... 22 table 5.1 i/o peripherals signal names ................................ ................................ ............................... 29 table 5.2 group 0 ................................ ................................ ................................ ................................ 31 table 5.3 group 1 ................................ ................................ ................................ ................................ 32 table 5.4 group 2 ................................ ................................ ................................ ................................ 33 table 5.5 group 3 ................................ ................................ ................................ ................................ 34 table 6.1 data and control bus signal mode options C uart interface ................................ ................. 38 table 6.2 spi signal names ................................ ................................ ................................ .................. 39 table 6.3 - spi slave speeds ................................ ................................ ................................ ................ 40 table 6.4 - clock phase /polarity modes ................................ ................................ ................................ . 40 table 6.5 data and control bus signal mode options - spi slave interface ................................ ........... 42 table 6.6 spi command and status fields ................................ ................................ ............................ 44 table 6.7 spi command and status fields ................................ ................................ ............................ 49 table 6.8 spi setup bit encoding ................................ ................................ ................................ .......... 49 table 6.9 spi slave data timing ................................ ................................ ................................ ........... 50 table 6.10 spi master data read status bit ................................ ................................ .......................... 51 table 6.11 spi master data write status bit ................................ ................................ ......................... 51 table 6.12 spi status read byte C bit descriptions ................................ ................................ ............... 52 table 6.13 spi master signal names ................................ ................................ ................................ ..... 54 table 6.14 spi master timing ................................ ................................ ................................ ............... 55 table 6.15 debugger signal name ................................ ................................ ................................ ....... 56 table 6.16 data and control bus signal mode options - parallel fifo interface ................................ ..... 59 table 6.17 asynchronous fifo mode read / write timing ................................ ................................ ..... 60 table 6.18 synchronous fifo control signals ................................ ................................ ........................ 61 table 6.19 synchronous fifo mode read / write timing ................................ ................................ ...... 63 table 9.1 absolute ma ximum ratings ................................ ................................ ................................ ... 68 table 9.2 operating voltage and current ................................ ................................ .............................. 69 table 9.3 i/o pin characteristics ................................ ................................ ................................ ........... 69 table 9.4 usb i/o pin (usbdp, usbdm) characteristics ................................ ................................ ........ 70 table 9.5 crystal oscillator 1.8 volts dc characteristics ................................ ................................ ........ 70 table 9.6 esd and latch - up specifications ................................ ................................ ............................ 71 table 11.1 reflow profile parameter values ................................ ................................ .......................... 81 table 11.2 pack age reflow peak temperature ................................ ................................ ...................... 81 list of figures 86 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 figure 2.1 simplified vnc2 block diagram ................................ ................................ .............................. 3 figure 3.1 32 pin lqfp C top down view ................................ ................................ ............................... 7 figure 3.2 32 pin qfn C top down view ................................ ................................ ................................ 8 figure 3.3 48 pin lqfp C top down view ................................ ................................ ............................... 9 figure 3.4 48 pin qfn C top down view ................................ ................................ ............................... 10 figure 3.5 64 pin lqfp C top down view ................................ ................................ ............................. 11 figure 3.6 64 pin qfn C top down view ................................ ................................ ............................... 12 figure 3.7 schematic symbol 32 pin ................................ ................................ ................................ ..... 13 figure 3.8 schematic symbol 48 pin ................................ ................................ ................................ ..... 14 figure 3.9 schematic symbol 64 pin ................................ ................................ ................................ ..... 15 figure 5.1 iobus to group relationship - 64 pin ................................ ................................ ..................... 25 figure 5.2 iobus to uart, spi slave0 and spi master example ................................ ............................ 26 figure 5.3 iobus to uart, spi slave0 and spi master second example ................................ ................ 27 figure 5.4 iobus to uart, spi slave0 and spi master third example ................................ .................... 28 figure 5.5 vnc2 toolchain app wizard showing iomux configuration ................................ .................... 30 figure 5.6 uart example 64 pin ................................ ................................ ................................ ........... 35 figure 6.1 uart receive waveform ................................ ................................ ................................ ...... 36 figure 6.2 uart transmit w aveform ................................ ................................ ................................ .... 36 figure 6.3 - spi cpol cpha function ................................ ................................ ................................ .... 41 figure 6.4 spi slave block diagram ................................ ................................ ................................ ...... 41 figure 6.5 full duplex data master write ................................ ................................ .............................. 43 figure 6.6 full duplex data master read ................................ ................................ .............................. 43 figure 6.7 spi co mmand and status structure ................................ ................................ ..................... 44 figure 6.8 half duplex data master write ................................ ................................ ............................. 45 figure 6.9 half duplex data master read ................................ ................................ .............................. 45 figure 6.10 half duplex 3 - pin data master write ................................ ................................ .................. 46 figure 6.11 half duplex 3 - pin data master read ................................ ................................ ................... 46 figure 6.12 unmanaged mode transfer diagram ................................ ................................ ................... 47 figure 6.13 vnc1l mode data write ................................ ................................ ................................ ..... 48 figure 6.14 vnc1l mode data read ................................ ................................ ................................ ...... 48 figure 6.15 vnc1l compatible spi command and status structure ................................ ...................... 49 figure 6.16 spi slave mode timing ................................ ................................ ................................ ....... 50 figure 6.17 spi master data read (vnc2 slave mode) ................................ ................................ .......... 51 figure 6.18 spi slave mode data write ................................ ................................ ................................ . 52 figure 6.19 spi slave mode status read ................................ ................................ .............................. 52 figure 6.20 spi master block diagram ................................ ................................ ................................ ... 53 figure 6.21 typical spi master timing ................................ ................................ ................................ .. 55 figure 6.22 asynchronous fifo mode read / write cycle ................................ ................................ ..... 60 figure 6.23 synchronous fifo mode read / write cycle ................................ ................................ ....... 62 figure 6.24 pwm C timing diagram ................................ ................................ ................................ ...... 64 figure 6.25 gpio port groups ................................ ................................ ................................ ............... 64 figure 7.1 usb modes ................................ ................................ ................................ .......................... 65 figure 10.1 vnc2 schematic (mcu C uart interface) ................................ ................................ ........... 72 figure 11.1 package markings ................................ ................................ ................................ .............. 73 87 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 figure 11.2 markings C 32 qfn ................................ ................................ ................................ ............. 73 figure 11.3 lqfp - 32 package dimensions ................................ ................................ ............................. 74 f igure 11.4 qfn - 32 package dimensions ................................ ................................ .............................. 75 figure 11.5 lqfp - 48 package dimensions ................................ ................................ ............................. 76 figure 11.6 64 pin lqfp package details ................................ ................................ .............................. 78 figure 11.7 64 pin qfn package details ................................ ................................ ................................ 79 figure 11.8 all packages reflow solder profile ................................ ................................ ...................... 80 88 c opyright ? future t ec hnology d evic es i nternational l imited datasheet vinculum - ii embedded dual usb host controller ic v ers ion 1 .7 d oc ument n o.: ft _000138 c learance n o.: ft d i# 1 43 appendi x c C revision history document title: vinculum - ii embedded dual usb host controller ic datasheet document reference no.: ft _000138 clearance no.: ftdi# 143 document folder : v inculum - ii document feedback: send feedback revision ch anges date prelim data sheet released as preliminary C subject to change before revised part numbers to rev b in section 1.2, added notes to C |
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